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Computational intelligence-based testing for noise and robustness analysis

  • Infineon Technologies AG

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Interconnect and power supply noise (PSN) is becoming more severe as technology scales, and can cause signal distortion and increase gate delay. This can further result in improper circuit operation. This paper describes a novel computational intelligence with ultra-short worst case test flow concept to detect a hang-up in a pseudo-SRAM test chip with asynchronous operation and hidden refresh, Package parasitics are found to be the cause of the failure, and debugging is performed by modification of the power network. This method allows finding worst case tests and identifying design weaknesses efficiently.

Original languageEnglish
Title of host publicationProceedings of the 2005 IEEE International Conference on Computational Intelligence for Measurement Systems and Applications, CIMSA 2005
Pages279-284
Number of pages6
DOIs
StatePublished - 2005
Event2005 IEEE International Conference on Computational Intelligence for Measurement Systems and Applications, CIMSA 2005 - Giardini, Naxos, Italy
Duration: 20 Jul 200522 Jul 2005

Publication series

NameProceedings of the 2005 IEEE International Conference on Computational Intelligence for Measurement Systems and Applications, CIMSA 2005
Volume2005

Conference

Conference2005 IEEE International Conference on Computational Intelligence for Measurement Systems and Applications, CIMSA 2005
Country/TerritoryItaly
CityGiardini, Naxos
Period20/07/0522/07/05

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