TY - GEN
T1 - Compact Ferroelectric Programmable Majority Gate for Compute-in-Memory Applications
AU - Deng, Shan
AU - Benkhelifa, Mahdi
AU - Thomann, Simon
AU - Faris, Zubair
AU - Zhao, Zijian
AU - Huang, Tzu Jung
AU - Xu, Yixin
AU - Narayanan, Vijaykrishnan
AU - Ni, Kai
AU - Amrouch, Hussam
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - In this work, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.
AB - In this work, a compact and novel ferroelectric (FE) programmable majority gate is proposed and its novel application in Binary Neural Network (BNNs) is investigated. We demonstrate: i) by integrating N metal-ferroelectric-metal (MFM) capacitors on the gate of a transistor (1T-N-MFM structure), a nonvolatile and programmable majority (MAJ) gate that performs MAJ of AND between the gate input and polarization is realized; ii) validation the functionality of our 3-input MAJ of AND gate through comprehensive theoretical and experimental investigations; iii) a compact implementation of 3-input MAJ of XNOR gate that leverages only five of our 3-input MAJ of AND gates connected in parallel; iv) application of MAJ of XNOR gates to replace the XNOR gates and the first layer of the adder tree in the BNNs for up to 21x area saving on top of eliminating the energy-hungry memory accesses due to the compute-in-memory nature.
UR - http://www.scopus.com/inward/record.url?scp=85147524356&partnerID=8YFLogxK
U2 - 10.1109/IEDM45625.2022.10019400
DO - 10.1109/IEDM45625.2022.10019400
M3 - Conference contribution
AN - SCOPUS:85147524356
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 3671
EP - 3674
BT - 2022 International Electron Devices Meeting, IEDM 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 International Electron Devices Meeting, IEDM 2022
Y2 - 3 December 2022 through 7 December 2022
ER -