Clock skew determination from parameter variations at chip and wafer level

Stephan Sauter; D. Cousinard; Roland Thewes; D. Schmitt-Landsiedel; Werner Weber

Clock skew determination from parameter variations at chip and wafer level

Stephan Sauter, D. Cousinard, Roland Thewes, D. Schmitt-Landsiedel, Werner Weber

Siemens AG

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

Clock skews are determined by measuring device and metal line parameters as a function of position over chip and wafer. Experimental results are separated into a basic random fluctuation part and processing related contributions on chip and wafer level. Different clock tree circuits are simulated based on the measured data, and characterized with the delay, power consumption, layout area and temperature as parameters. Simulations yield a worst case skew of 42ps for a 0.25μm process and a metal3 H-clock tree.

Original language	English
Pages	7-9
Number of pages	3
State	Published - 1999
Externally published	Yes
Event	Proceedings of the 1999 4th International Workshop on Statistical Metrology (1999 IWSM) - Kyoto, Jpn Duration: 12 Jun 1999 → 12 Jun 1999

Conference

Conference	Proceedings of the 1999 4th International Workshop on Statistical Metrology (1999 IWSM)
City	Kyoto, Jpn
Period	12/06/99 → 12/06/99

Cite this

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title = "Clock skew determination from parameter variations at chip and wafer level",

abstract = "Clock skews are determined by measuring device and metal line parameters as a function of position over chip and wafer. Experimental results are separated into a basic random fluctuation part and processing related contributions on chip and wafer level. Different clock tree circuits are simulated based on the measured data, and characterized with the delay, power consumption, layout area and temperature as parameters. Simulations yield a worst case skew of 42ps for a 0.25μm process and a metal3 H-clock tree.",

author = "Stephan Sauter and D. Cousinard and Roland Thewes and D. Schmitt-Landsiedel and Werner Weber",

year = "1999",

language = "English",

pages = "7--9",

note = "Proceedings of the 1999 4th International Workshop on Statistical Metrology (1999 IWSM) ; Conference date: 12-06-1999 Through 12-06-1999",

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T1 - Clock skew determination from parameter variations at chip and wafer level

AU - Sauter, Stephan

AU - Cousinard, D.

AU - Thewes, Roland

AU - Schmitt-Landsiedel, D.

AU - Weber, Werner

PY - 1999

Y1 - 1999

N2 - Clock skews are determined by measuring device and metal line parameters as a function of position over chip and wafer. Experimental results are separated into a basic random fluctuation part and processing related contributions on chip and wafer level. Different clock tree circuits are simulated based on the measured data, and characterized with the delay, power consumption, layout area and temperature as parameters. Simulations yield a worst case skew of 42ps for a 0.25μm process and a metal3 H-clock tree.

AB - Clock skews are determined by measuring device and metal line parameters as a function of position over chip and wafer. Experimental results are separated into a basic random fluctuation part and processing related contributions on chip and wafer level. Different clock tree circuits are simulated based on the measured data, and characterized with the delay, power consumption, layout area and temperature as parameters. Simulations yield a worst case skew of 42ps for a 0.25μm process and a metal3 H-clock tree.

UR - http://www.scopus.com/inward/record.url?scp=0033313935&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0033313935

SP - 7

EP - 9

T2 - Proceedings of the 1999 4th International Workshop on Statistical Metrology (1999 IWSM)

Y2 - 12 June 1999 through 12 June 1999

ER -

Clock skew determination from parameter variations at chip and wafer level

Abstract

Conference

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