Circuit line minimization in the HDL-based synthesis of reversible logic

In the last decade, reversible circuits have been extensively investigated due to their application in emerging areas such as quantum computation or low-power design. In the past, synthesis of reversible circuits was lifted from the Boolean level to approaches exploiting hardware description languages. However, existing HDL synthesizers lead to circuits with a significant number of additional lines. In this work, we focus on the reduction of additional circuit lines which are caused by buffering intermediate results. We propose an approach that reuses these lines as soon as the intermediate results are not required anymore. Experiments confirm that this approach decreases the number of circuit lines by up to two orders of magnitude and 60% on average.