Circuit and architectural optimization of static memories

Veronika Eisele; Doris Schmitt-Landsiedel

doi:10.1109/ESSCIRC.1992.5468385

Circuit and architectural optimization of static memories

Veronika Eisele
, Doris Schmitt-Landsiedel

Siemens AG
Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A new CAD environment for the design optimization of static RAMs has been developped. The optimal memory architecture is determined in varying the segmentation of the cell array. Optimal decoding and sensing circuits are chosen from a library. Transistor dimensions are optimized with respect to delay, area and power using analytical optimization techniques. The methods can be applied to all kinds of RAMs, significantly improving the efficiency and flexibility of the memory design process.

Original language	English
Title of host publication	ESSCIRC 1992 - 18th European Solid-State Circuits Conference, Proceedings
Publisher	IEEE Computer Society
Pages	139-140
Number of pages	2
ISBN (Electronic)	8798423207
DOIs	https://doi.org/10.1109/ESSCIRC.1992.5468385
State	Published - 1992
Externally published	Yes
Event	18th European Solid-State Circuits Conference, ESSCIRC 1992 - Copenhagen, Denmark Duration: 21 Sep 1992 → 23 Sep 1992

Publication series

Name	European Solid-State Circuits Conference
Volume	1992-September
ISSN (Print)	1930-8833

Conference

Conference	18th European Solid-State Circuits Conference, ESSCIRC 1992
Country/Territory	Denmark
City	Copenhagen
Period	21/09/92 → 23/09/92

Access to Document

10.1109/ESSCIRC.1992.5468385

Cite this

@inproceedings{95f9b85c55fc423c8c1642a64193a9e8,

title = "Circuit and architectural optimization of static memories",

abstract = "A new CAD environment for the design optimization of static RAMs has been developped. The optimal memory architecture is determined in varying the segmentation of the cell array. Optimal decoding and sensing circuits are chosen from a library. Transistor dimensions are optimized with respect to delay, area and power using analytical optimization techniques. The methods can be applied to all kinds of RAMs, significantly improving the efficiency and flexibility of the memory design process.",

author = "Veronika Eisele and Doris Schmitt-Landsiedel",

note = "Publisher Copyright: {\textcopyright} 1992 European Solid-State Circuits Conference.; 18th European Solid-State Circuits Conference, ESSCIRC 1992 ; Conference date: 21-09-1992 Through 23-09-1992",

year = "1992",

doi = "10.1109/ESSCIRC.1992.5468385",

language = "English",

series = "European Solid-State Circuits Conference",

publisher = "IEEE Computer Society",

pages = "139--140",

booktitle = "ESSCIRC 1992 - 18th European Solid-State Circuits Conference, Proceedings",

}

Eisele, V & Schmitt-Landsiedel, D 1992, Circuit and architectural optimization of static memories. in ESSCIRC 1992 - 18th European Solid-State Circuits Conference, Proceedings., 5468385, European Solid-State Circuits Conference, vol. 1992-September, IEEE Computer Society, pp. 139-140, 18th European Solid-State Circuits Conference, ESSCIRC 1992, Copenhagen, Denmark, 21/09/92. https://doi.org/10.1109/ESSCIRC.1992.5468385

Circuit and architectural optimization of static memories. / Eisele, Veronika; Schmitt-Landsiedel, Doris.
ESSCIRC 1992 - 18th European Solid-State Circuits Conference, Proceedings. IEEE Computer Society, 1992. p. 139-140 5468385 (European Solid-State Circuits Conference; Vol. 1992-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

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AU - Eisele, Veronika

AU - Schmitt-Landsiedel, Doris

PY - 1992

Y1 - 1992

N2 - A new CAD environment for the design optimization of static RAMs has been developped. The optimal memory architecture is determined in varying the segmentation of the cell array. Optimal decoding and sensing circuits are chosen from a library. Transistor dimensions are optimized with respect to delay, area and power using analytical optimization techniques. The methods can be applied to all kinds of RAMs, significantly improving the efficiency and flexibility of the memory design process.

AB - A new CAD environment for the design optimization of static RAMs has been developped. The optimal memory architecture is determined in varying the segmentation of the cell array. Optimal decoding and sensing circuits are chosen from a library. Transistor dimensions are optimized with respect to delay, area and power using analytical optimization techniques. The methods can be applied to all kinds of RAMs, significantly improving the efficiency and flexibility of the memory design process.

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U2 - 10.1109/ESSCIRC.1992.5468385

DO - 10.1109/ESSCIRC.1992.5468385

M3 - Conference contribution

AN - SCOPUS:85067672802

T3 - European Solid-State Circuits Conference

SP - 139

EP - 140

BT - ESSCIRC 1992 - 18th European Solid-State Circuits Conference, Proceedings

PB - IEEE Computer Society

T2 - 18th European Solid-State Circuits Conference, ESSCIRC 1992

Y2 - 21 September 1992 through 23 September 1992

ER -

Circuit and architectural optimization of static memories

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