Chip-level ESD simulation for fail detection and design guidance

S. Drüen, M. Streibl, F. Zängl, J. Schneider, U. Glaser, K. Esmark, W. Stadier, H. Gossner, D. Schmitt-Landsiedel

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations


A simulation approach and analysis method was studied that allows to address a class of ESD fails caused by an unfavorable setup of the chip supply concept and I/O cell ring. The high-complexity of chip-level ESD networks was handled with a Monte-Carlo like permutational approach. The integration of this method in the chip concept engineering and design flow was also discussed. The simulation method is able to predict critical ESD stress pin combinations and ESD fail positions even in complex digital and mixed signal designs.

Original languageEnglish
Pages (from-to)603-604
Number of pages2
JournalAnnual Proceedings - Reliability Physics (Symposium)
StatePublished - 2004
Event2004 IEEE International Reliability Physics Symposium Proceedings, 42nd Annual - Phoenix, AZ., United States
Duration: 25 Apr 200429 Apr 2004


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