TY - JOUR
T1 - Chip-level ESD simulation for fail detection and design guidance
AU - Drüen, S.
AU - Streibl, M.
AU - Zängl, F.
AU - Schneider, J.
AU - Glaser, U.
AU - Esmark, K.
AU - Stadier, W.
AU - Gossner, H.
AU - Schmitt-Landsiedel, D.
PY - 2004
Y1 - 2004
N2 - A simulation approach and analysis method was studied that allows to address a class of ESD fails caused by an unfavorable setup of the chip supply concept and I/O cell ring. The high-complexity of chip-level ESD networks was handled with a Monte-Carlo like permutational approach. The integration of this method in the chip concept engineering and design flow was also discussed. The simulation method is able to predict critical ESD stress pin combinations and ESD fail positions even in complex digital and mixed signal designs.
AB - A simulation approach and analysis method was studied that allows to address a class of ESD fails caused by an unfavorable setup of the chip supply concept and I/O cell ring. The high-complexity of chip-level ESD networks was handled with a Monte-Carlo like permutational approach. The integration of this method in the chip concept engineering and design flow was also discussed. The simulation method is able to predict critical ESD stress pin combinations and ESD fail positions even in complex digital and mixed signal designs.
UR - http://www.scopus.com/inward/record.url?scp=3042660034&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:3042660034
SN - 0099-9512
SP - 603
EP - 604
JO - Annual Proceedings - Reliability Physics (Symposium)
JF - Annual Proceedings - Reliability Physics (Symposium)
T2 - 2004 IEEE International Reliability Physics Symposium Proceedings, 42nd Annual
Y2 - 25 April 2004 through 29 April 2004
ER -