TY - GEN
T1 - Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits
AU - Van Santen, Victor M.
AU - Klemme, Florian
AU - Genssler, Paul R.
AU - Amrouch, Hussam
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Transistor and circuit reliability estimations face various challenges in both traditional and machine learning (ML) based approaches. In this work, we provide an overview of the toughest challenges faced by traditional physics-based reliability estimations, such as exposing sensitive transistor data, unfeasible execution times, material defect interactions, etc. Similarly, challenges for ML-based approaches are also highlighted, such as the aging recovery and history effects and high training effort. We present multiple solutions to overcome these challenges, such as high-performance physics-based aging models, history-aware machine learning, and techniques to reduce training data sets. We highlight, for the first time, that circuit reliability estimation can be achieved by bypassing the transistor level with ML-generated degraded standard cell libraries. Our high-performance aging models and circuit simulators provide speedups ranging from 4000x to 240,000x, while our standard cell ML techniques achieve 99.9% accuracy in less than 1 second inference time.
AB - Transistor and circuit reliability estimations face various challenges in both traditional and machine learning (ML) based approaches. In this work, we provide an overview of the toughest challenges faced by traditional physics-based reliability estimations, such as exposing sensitive transistor data, unfeasible execution times, material defect interactions, etc. Similarly, challenges for ML-based approaches are also highlighted, such as the aging recovery and history effects and high training effort. We present multiple solutions to overcome these challenges, such as high-performance physics-based aging models, history-aware machine learning, and techniques to reduce training data sets. We highlight, for the first time, that circuit reliability estimation can be achieved by bypassing the transistor level with ML-generated degraded standard cell libraries. Our high-performance aging models and circuit simulators provide speedups ranging from 4000x to 240,000x, while our standard cell ML techniques achieve 99.9% accuracy in less than 1 second inference time.
KW - Aging
KW - Bias Temperature Instability
KW - Circuit Reliability
KW - Degradation
KW - Hot-Carrier
KW - Machine Learning
KW - Reliability
KW - Self-Heating
KW - Transistor Reliability
UR - http://www.scopus.com/inward/record.url?scp=85179013967&partnerID=8YFLogxK
U2 - 10.1109/DFT59622.2023.10313528
DO - 10.1109/DFT59622.2023.10313528
M3 - Conference contribution
AN - SCOPUS:85179013967
T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
BT - 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
A2 - Cassano, Luca
A2 - Psarakis, Mihalis
A2 - Traiola, Marcello
A2 - Bosio, Alberto
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023
Y2 - 3 October 2023 through 5 October 2023
ER -