Cache efficiency and scalability on multi-core architectures

Thomas Müller, Carsten Trinitis, Jasmin Smajic

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Two electrical engineering applications from industry partners dealing with sparse matrices were analyzed regarding cache efficiency and scalability on modern multi core systems. Two different contemporary multi-core architectures have been investigated, namely Intel's Westmere and AMD's Magny-Cours. This paper can be regarded as a continuation of the investigations presented in [14] and [15]. In addition, the SuiteSparseQR library for efficiently computing QR factorizations of sparse matrices was evaluated regarding scalability and cache efficiency.

Original languageEnglish
Title of host publicationParallel Computing Technologies - 11th International Conference, PaCT 2011, Proceedings
Pages88-97
Number of pages10
DOIs
StatePublished - 2011
Externally publishedYes
Event11th International Conference on Parallel Computing Technologies, PaCT 2011 - Kazan, Russian Federation
Duration: 19 Sep 201123 Sep 2011

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume6873 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference11th International Conference on Parallel Computing Technologies, PaCT 2011
Country/TerritoryRussian Federation
CityKazan
Period19/09/1123/09/11

Keywords

  • Amdahl's Law
  • SuiteSparseQR
  • cache efficiency
  • multi-core
  • sparse matrix
  • thread-to-core assignment

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