Built-in self test architectures for multistage interconnection networks

E. Bernard; S. Simon; J. A. Nossek

doi:10.1109/EDTC.1996.494145

Built-in self test architectures for multistage interconnection networks

E. Bernard, S. Simon, J. A. Nossek

Chair of Circuit Theory and Signal Processing (2008 — 2021)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A novel built-in self test architecture for locally controlled cube-type N × N multistage interconnection networks (MINs) is presented. First, a state-based pseudoexhaustive test procedure for this class of MINs is outlined. Then, a labelling algorithm on a binary n-cube is described which generates the necessary inputs for the tests. From the dependence graph of this algorithm a tree architecture is derived which results in a hardware overhead of O(1/log N).

Original language	English
Title of host publication	Proceedings of the 1996 European Conference on Design and Test, EDTC 1996
Publisher	Association for Computing Machinery, Inc
Pages	176-180
Number of pages	5
ISBN (Electronic)	0818674237, 9780818674235
DOIs	https://doi.org/10.1109/EDTC.1996.494145
State	Published - 11 Mar 1996
Event	1996 European Conference on Design and Test, EDTC 1996 - Paris, France Duration: 11 Mar 1996 → 14 Mar 1996

Publication series

Name	Proceedings of the 1996 European Conference on Design and Test, EDTC 1996

Conference

Conference	1996 European Conference on Design and Test, EDTC 1996
Country/Territory	France
City	Paris
Period	11/03/96 → 14/03/96

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10.1109/EDTC.1996.494145

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Bernard, E., Simon, S., & Nossek, J. A. (1996). Built-in self test architectures for multistage interconnection networks. In Proceedings of the 1996 European Conference on Design and Test, EDTC 1996 (pp. 176-180). Article 494145 (Proceedings of the 1996 European Conference on Design and Test, EDTC 1996). Association for Computing Machinery, Inc. https://doi.org/10.1109/EDTC.1996.494145

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Bernard, E, Simon, S & Nossek, JA 1996, Built-in self test architectures for multistage interconnection networks. in Proceedings of the 1996 European Conference on Design and Test, EDTC 1996., 494145, Proceedings of the 1996 European Conference on Design and Test, EDTC 1996, Association for Computing Machinery, Inc, pp. 176-180, 1996 European Conference on Design and Test, EDTC 1996, Paris, France, 11/03/96. https://doi.org/10.1109/EDTC.1996.494145

Built-in self test architectures for multistage interconnection networks. / Bernard, E.; Simon, S.; Nossek, J. A.
Proceedings of the 1996 European Conference on Design and Test, EDTC 1996. Association for Computing Machinery, Inc, 1996. p. 176-180 494145 (Proceedings of the 1996 European Conference on Design and Test, EDTC 1996).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Built-in self test architectures for multistage interconnection networks

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