BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array-including Sense Amplifiers and Write Drivers-under Processor Activity

Victor M. Van Santen; Simon Thomann; Chaitanya Pasupuleti; Paul R. Genssler; Narendra Gangwar; Uma Sharma; Jorg Henkel; Souvik Mahapatra; Hussam Amrouch

doi:10.1109/IRPS45951.2020.9128342

BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array-including Sense Amplifiers and Write Drivers-under Processor Activity

Victor M. Van Santen, Simon Thomann, Chaitanya Pasupuleti, Paul R. Genssler, Narendra Gangwar, Uma Sharma, Jorg Henkel, Souvik Mahapatra, Hussam Amrouch

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

20 Scopus citations

Abstract

For the first time, we present a study of BTI and HCD degradation in a 32 × 64 cell SRAM array including Sense Amplifiers (SA), Write Drivers (WD) and pre-charging circuitry (one each for 64 columns) stimulated by the workload-induced activity of a commercial processor. In under 2 hours, our fully automated framework employs the extracted activities to create voltage waveforms used in SPICE simulations (SRAM Array, SA, WD) and degrades transistors using their individual exhibited voltages as stimuli in BTI and HCD models. We support different temperatures, supply voltages (including DVFS), SRAM, SA and WD designs.

Original language	English
Title of host publication	2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728131993
DOIs	https://doi.org/10.1109/IRPS45951.2020.9128342
State	Published - Apr 2020
Externally published	Yes
Event	2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Virtual, Online, United States Duration: 28 Apr 2020 → 30 May 2020

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
Volume	2020-April
ISSN (Print)	1541-7026

Conference

Conference	2020 IEEE International Reliability Physics Symposium, IRPS 2020
Country/Territory	United States
City	Virtual, Online
Period	28/04/20 → 30/05/20

Keywords

Aging
BTI
Bias Temperature Instability
Circuit Reliability
HCD
HCD
Hot Carrier
Memory
SRAM

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10.1109/IRPS45951.2020.9128342

Cite this

Van Santen, V. M., Thomann, S., Pasupuleti, C., Genssler, P. R., Gangwar, N., Sharma, U., Henkel, J., Mahapatra, S., & Amrouch, H. (2020). BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array-including Sense Amplifiers and Write Drivers-under Processor Activity. In 2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings Article 9128342 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2020-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS45951.2020.9128342

Van Santen, Victor M. ; Thomann, Simon ; Pasupuleti, Chaitanya et al. / BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array-including Sense Amplifiers and Write Drivers-under Processor Activity. 2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (IEEE International Reliability Physics Symposium Proceedings).

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title = "BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array-including Sense Amplifiers and Write Drivers-under Processor Activity",

abstract = "For the first time, we present a study of BTI and HCD degradation in a 32 × 64 cell SRAM array including Sense Amplifiers (SA), Write Drivers (WD) and pre-charging circuitry (one each for 64 columns) stimulated by the workload-induced activity of a commercial processor. In under 2 hours, our fully automated framework employs the extracted activities to create voltage waveforms used in SPICE simulations (SRAM Array, SA, WD) and degrades transistors using their individual exhibited voltages as stimuli in BTI and HCD models. We support different temperatures, supply voltages (including DVFS), SRAM, SA and WD designs.",

keywords = "Aging, BTI, Bias Temperature Instability, Circuit Reliability, HCD, HCD, Hot Carrier, Memory, SRAM",

author = "{Van Santen}, {Victor M.} and Simon Thomann and Chaitanya Pasupuleti and Genssler, {Paul R.} and Narendra Gangwar and Uma Sharma and Jorg Henkel and Souvik Mahapatra and Hussam Amrouch",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE International Reliability Physics Symposium, IRPS 2020 ; Conference date: 28-04-2020 Through 30-05-2020",

year = "2020",

month = apr,

doi = "10.1109/IRPS45951.2020.9128342",

language = "English",

series = "IEEE International Reliability Physics Symposium Proceedings",

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Van Santen, VM, Thomann, S, Pasupuleti, C, Genssler, PR, Gangwar, N, Sharma, U, Henkel, J, Mahapatra, S & Amrouch, H 2020, BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array-including Sense Amplifiers and Write Drivers-under Processor Activity. in 2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings., 9128342, IEEE International Reliability Physics Symposium Proceedings, vol. 2020-April, Institute of Electrical and Electronics Engineers Inc., 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Virtual, Online, United States, 28/04/20. https://doi.org/10.1109/IRPS45951.2020.9128342

BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array-including Sense Amplifiers and Write Drivers-under Processor Activity. / Van Santen, Victor M.; Thomann, Simon; Pasupuleti, Chaitanya et al.
2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9128342 (IEEE International Reliability Physics Symposium Proceedings; Vol. 2020-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Van Santen, Victor M.

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AU - Pasupuleti, Chaitanya

AU - Genssler, Paul R.

AU - Gangwar, Narendra

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AU - Mahapatra, Souvik

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AB - For the first time, we present a study of BTI and HCD degradation in a 32 × 64 cell SRAM array including Sense Amplifiers (SA), Write Drivers (WD) and pre-charging circuitry (one each for 64 columns) stimulated by the workload-induced activity of a commercial processor. In under 2 hours, our fully automated framework employs the extracted activities to create voltage waveforms used in SPICE simulations (SRAM Array, SA, WD) and degrades transistors using their individual exhibited voltages as stimuli in BTI and HCD models. We support different temperatures, supply voltages (including DVFS), SRAM, SA and WD designs.

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Van Santen VM, Thomann S, Pasupuleti C, Genssler PR, Gangwar N, Sharma U et al. BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array-including Sense Amplifiers and Write Drivers-under Processor Activity. In 2020 IEEE International Reliability Physics Symposium, IRPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9128342. (IEEE International Reliability Physics Symposium Proceedings). doi: 10.1109/IRPS45951.2020.9128342

BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array-including Sense Amplifiers and Write Drivers-under Processor Activity

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