Block sequential CORDIC architectures

In the design of VLSI circuits for parallel algorithms very often a trade-off between hardware complexity and execution speed has to be made, which results in a decision between bit-parallel and bit-serial arithmetic implementations. We use a data format, called block data format, which covers the whole range from bit-serial to bit-parallel processing and thus offers more flexibility in the decision process. We propose architectures for partitioned CORDIC units which are described using the blockwidth of the partitioned data record as a parameter and which are therefore suited for a possible automatic layout generation of such modules. The partitioned data arrays additionally lead to a reduction of the maximal shift distance between two CORDIC stages from O(p) to O(√p), where p is the wordlength of the operands, and thus reduce the maximal propagation delay.