Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive

Mihail Jefremow; Thomas Kern; Ulrich Backhausen; Christian Peters; Christoph Parzinger; Christoph Roll; Stephan Kassenetter; Stefanie Thierold; Doris Schmitt-Landsiedel

doi:10.1109/ISSCC.2012.6177076

Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive

Mihail Jefremow, Thomas Kern, Ulrich Backhausen, Christian Peters, Christoph Parzinger, Christoph Roll, Stephan Kassenetter, Stefanie Thierold, Doris Schmitt-Landsiedel

Medicine and Health

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

25 Scopus citations

Abstract

The markets trends in the automotive industry of efficiency, safety and standardization, demand an increase in system performance (e.g., system frequency or by using multi core architectures) in microcontrollers for automotive powertrain applications. Since embedded nonvolatile memory is an essential part of such an SoC, the memory read speed must increase at the same rate to achieve best possible overall system performance. A further trend is that memory size is increasing with every new technology node to support complex algorithms required for real-time automotive applications. Larger memory sizes lead typically to an increase of the bitline (BL) capacitance, which is one of the most critical parameters for read performance of a memory array.

Original language	English
Title of host publication	2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
Pages	428-429
Number of pages	2
DOIs	https://doi.org/10.1109/ISSCC.2012.6177076
State	Published - 2012
Event	59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States Duration: 19 Feb 2012 → 23 Feb 2012

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	55
ISSN (Print)	0193-6530

Conference

Conference	59th International Solid-State Circuits Conference, ISSCC 2012
Country/Territory	United States
City	San Francisco, CA
Period	19/02/12 → 23/02/12

Access to Document

10.1109/ISSCC.2012.6177076

Cite this

Jefremow, M., Kern, T., Backhausen, U., Peters, C., Parzinger, C., Roll, C., Kassenetter, S., Thierold, S., & Schmitt-Landsiedel, D. (2012). Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers (pp. 428-429). Article 6177076 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55). https://doi.org/10.1109/ISSCC.2012.6177076

Jefremow, Mihail ; Kern, Thomas ; Backhausen, Ulrich et al. / Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive. 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. pp. 428-429 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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title = "Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive",

abstract = "The markets trends in the automotive industry of efficiency, safety and standardization, demand an increase in system performance (e.g., system frequency or by using multi core architectures) in microcontrollers for automotive powertrain applications. Since embedded nonvolatile memory is an essential part of such an SoC, the memory read speed must increase at the same rate to achieve best possible overall system performance. A further trend is that memory size is increasing with every new technology node to support complex algorithms required for real-time automotive applications. Larger memory sizes lead typically to an increase of the bitline (BL) capacitance, which is one of the most critical parameters for read performance of a memory array.",

author = "Mihail Jefremow and Thomas Kern and Ulrich Backhausen and Christian Peters and Christoph Parzinger and Christoph Roll and Stephan Kassenetter and Stefanie Thierold and Doris Schmitt-Landsiedel",

year = "2012",

doi = "10.1109/ISSCC.2012.6177076",

language = "English",

isbn = "9781467303736",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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note = "59th International Solid-State Circuits Conference, ISSCC 2012 ; Conference date: 19-02-2012 Through 23-02-2012",

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Jefremow, M, Kern, T, Backhausen, U, Peters, C, Parzinger, C, Roll, C, Kassenetter, S, Thierold, S & Schmitt-Landsiedel, D 2012, Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive. in 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers., 6177076, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 55, pp. 428-429, 59th International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, United States, 19/02/12. https://doi.org/10.1109/ISSCC.2012.6177076

Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive. / Jefremow, Mihail; Kern, Thomas; Backhausen, Ulrich et al.
2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. p. 428-429 6177076 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - The markets trends in the automotive industry of efficiency, safety and standardization, demand an increase in system performance (e.g., system frequency or by using multi core architectures) in microcontrollers for automotive powertrain applications. Since embedded nonvolatile memory is an essential part of such an SoC, the memory read speed must increase at the same rate to achieve best possible overall system performance. A further trend is that memory size is increasing with every new technology node to support complex algorithms required for real-time automotive applications. Larger memory sizes lead typically to an increase of the bitline (BL) capacitance, which is one of the most critical parameters for read performance of a memory array.

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Jefremow M, Kern T, Backhausen U, Peters C, Parzinger C, Roll C et al. Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. p. 428-429. 6177076. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2012.6177076

Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive

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