TY - GEN
T1 - BiSME
T2 - 29th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2018
AU - Shankar, Subramanian Shiva
AU - Pinxing, Lin
AU - Herkersdorf, Andreas
AU - Wild, Thomas
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/8/23
Y1 - 2018/8/23
N2 - Hardware acceleration of signature matching is essential to perform content aware networking at predictable rates in modern network processors. Existing hardware accelerators either cannot perform signature matching at predictable rates due to the storage organization of the signatures or do not compress the signatures effectively resulting in inefficient on-chip memory usage. Addressing these problems, a bitmap based signature matching engine called BiSME is proposed in this paper, which is a flexible, programmable and scalable hardware coprocessor to perform signature matching at fixed, but guaranteed rates. The storage architectures proposed as part of BiSME, allows to efficiently store the compressed signatures in a flexible and programmable manner in on-chip memories. Each BiSME instance is fine-tuned to perform signature matching at 9.3 Gbps, with multiple instances capable of supporting increasing signature counts as well as increasing throughput. The BiSME was synthesized on a commercial 28nm technology library and only occupies 1.43 mm2of silicon area and consumes 155mW of power. The BiSME hardware implementation was thoroughly verified on the Cadence Palladium platform. Over 2GB of network traffic was injected simultaneously into BiSME and a software based signature matching solution and the identical signature matching results further validated the correctness of the design.
AB - Hardware acceleration of signature matching is essential to perform content aware networking at predictable rates in modern network processors. Existing hardware accelerators either cannot perform signature matching at predictable rates due to the storage organization of the signatures or do not compress the signatures effectively resulting in inefficient on-chip memory usage. Addressing these problems, a bitmap based signature matching engine called BiSME is proposed in this paper, which is a flexible, programmable and scalable hardware coprocessor to perform signature matching at fixed, but guaranteed rates. The storage architectures proposed as part of BiSME, allows to efficiently store the compressed signatures in a flexible and programmable manner in on-chip memories. Each BiSME instance is fine-tuned to perform signature matching at 9.3 Gbps, with multiple instances capable of supporting increasing signature counts as well as increasing throughput. The BiSME was synthesized on a commercial 28nm technology library and only occupies 1.43 mm2of silicon area and consumes 155mW of power. The BiSME hardware implementation was thoroughly verified on the Cadence Palladium platform. Over 2GB of network traffic was injected simultaneously into BiSME and a software based signature matching solution and the identical signature matching results further validated the correctness of the design.
KW - Content Aware Networking
KW - Deep Packet Inspection
KW - Finite Automaton
KW - Pattern Matching
KW - Regular Expressions
KW - Signature Matching
KW - Transition Compression
UR - http://www.scopus.com/inward/record.url?scp=85053478245&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2018.8445090
DO - 10.1109/ASAP.2018.8445090
M3 - Conference contribution
AN - SCOPUS:85053478245
SN - 9781538674796
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
BT - 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2018
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 10 July 2018 through 12 July 2018
ER -