TY - GEN
T1 - Automatically comparing analog behavior using Earth Mover's Distance
AU - Rath, Alexander W.
AU - Simon, Sebastian
AU - Esen, Volkan
AU - Ecker, Wolfgang
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/11/22
Y1 - 2016/11/22
N2 - Evaluating the outcome of analog simulations is a common, mostly manually carried out task in the pre-silicon verification process of mixed-signal ICs. Its non-automated nature makes it an error-prone and time-consuming procedure. For this very reason, we introduce a novel approach for performing this evaluation automatically resulting in significantly reduced turnaround times as well as a considerably increased reliability of verification results. The presented concept is motivated by an algorithm that is used in optical pattern recognition and is called Earth Mover's Distance. Furthermore, we compare our approach with already existing algorithms, namely Fréchet Distance and Pearson Coefficient, in order to analyze its capability. Finally, we present a case study in which we prove the algorithm by applying it to the results of a mixed-signal simulation at chip-level demonstrating the efficiency of our approach.
AB - Evaluating the outcome of analog simulations is a common, mostly manually carried out task in the pre-silicon verification process of mixed-signal ICs. Its non-automated nature makes it an error-prone and time-consuming procedure. For this very reason, we introduce a novel approach for performing this evaluation automatically resulting in significantly reduced turnaround times as well as a considerably increased reliability of verification results. The presented concept is motivated by an algorithm that is used in optical pattern recognition and is called Earth Mover's Distance. Furthermore, we compare our approach with already existing algorithms, namely Fréchet Distance and Pearson Coefficient, in order to analyze its capability. Finally, we present a case study in which we prove the algorithm by applying it to the results of a mixed-signal simulation at chip-level demonstrating the efficiency of our approach.
UR - http://www.scopus.com/inward/record.url?scp=85006759425&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2016.7753556
DO - 10.1109/VLSI-SoC.2016.7753556
M3 - Conference contribution
AN - SCOPUS:85006759425
T3 - 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
BT - 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
Y2 - 26 September 2016 through 28 September 2016
ER -