Automatic test pattern generation for multiple missing gate faults in reversible circuits work in progress report

Anmol Prakash Surhonne, Anupam Chattopadhyay, Robert Wille

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Logical reversibility is the basis for emerging technologies like quantum computing, may be used for certain aspects of low-power design, and has been proven beneficial for the design of encoding/decoding devices. Testing of circuits has been a major concern to verify the integrity of the implementation of the circuit. In this paper, we propose the main ideas of an ATPG method for detecting two missing gate faults. To that effect, we propose a systematic flow using Binary Decision Diagrams (BDDs). Initial experimental results demonstrate the efficacy of the proposed algorithms in terms of scalability and coverage of all testable faults.

Original languageEnglish
Title of host publicationReversible Computation - 9th International Conference, RC 2017, Proceedings
EditorsHafizur Rahaman, Iain Phillips
PublisherSpringer Verlag
Pages176-182
Number of pages7
ISBN (Print)9783319599359
DOIs
StatePublished - 2017
Externally publishedYes
Event9th International Conference on Reversible Computation, RC 2017 - Kolkata, India
Duration: 6 Jul 20177 Jul 2017

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume10301 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference9th International Conference on Reversible Computation, RC 2017
Country/TerritoryIndia
CityKolkata
Period6/07/177/07/17

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