Automatic generation of hierarchical placement rules for analog integrated circuits

Michael Eick; Martin Strasser; Helmut E. Graeb; Ulf Schlichtmann

doi:10.1145/1735023.1735039

Automatic generation of hierarchical placement rules for analog integrated circuits

Michael Eick
, Martin Strasser
, Helmut E. Graeb
, Ulf Schlichtmann

Chair of Electronic Design Automation

Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

14 Scopus citations

Abstract

This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement. The netlist, a library of building blocks and a symmetry analysis are the basis to determine a constraint requirement graph, which comprises five types of proximity, matching and symmetry constraints. According to the priority of the constraint types, a hierarchical partitioning of the circuit into matching, proximity and symmetry groups is then automatically computed and forwarded to a state-of-the-art placement tool. Based on experimental results, we show that the new approach generates more placement rules and leads to better circuit performances according to post-layout simulation compared to a commercial approach.

Original language	English
Title of host publication	ISPD'10 - Proceedings of the 2010 ACM International Symposium on Physical Design
Pages	47-54
Number of pages	8
DOIs	https://doi.org/10.1145/1735023.1735039
State	Published - 2010
Event	2010 ACM International Symposium on Physical Design, ISPD'10 - San Francisco, CA, United States Duration: 14 Mar 2010 → 17 Mar 2010

Publication series

Name	Proceedings of the International Symposium on Physical Design

Conference

Conference	2010 ACM International Symposium on Physical Design, ISPD'10
Country/Territory	United States
City	San Francisco, CA
Period	14/03/10 → 17/03/10

Keywords

Analog integrated circuits
Constraints
Hierarchical placement rules
Placement

Access to Document

10.1145/1735023.1735039

Cite this

@inproceedings{37433ae6d8ca466da2c226ed4fd169dc,

title = "Automatic generation of hierarchical placement rules for analog integrated circuits",

abstract = "This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement. The netlist, a library of building blocks and a symmetry analysis are the basis to determine a constraint requirement graph, which comprises five types of proximity, matching and symmetry constraints. According to the priority of the constraint types, a hierarchical partitioning of the circuit into matching, proximity and symmetry groups is then automatically computed and forwarded to a state-of-the-art placement tool. Based on experimental results, we show that the new approach generates more placement rules and leads to better circuit performances according to post-layout simulation compared to a commercial approach.",

keywords = "Analog integrated circuits, Constraints, Hierarchical placement rules, Placement",

author = "Michael Eick and Martin Strasser and Graeb, \{Helmut E.\} and Ulf Schlichtmann",

year = "2010",

doi = "10.1145/1735023.1735039",

language = "English",

isbn = "9781605589206",

series = "Proceedings of the International Symposium on Physical Design",

pages = "47--54",

booktitle = "ISPD'10 - Proceedings of the 2010 ACM International Symposium on Physical Design",

note = "2010 ACM International Symposium on Physical Design, ISPD'10 ; Conference date: 14-03-2010 Through 17-03-2010",

}

Eick, M, Strasser, M, Graeb, HE & Schlichtmann, U 2010, Automatic generation of hierarchical placement rules for analog integrated circuits. in ISPD'10 - Proceedings of the 2010 ACM International Symposium on Physical Design. Proceedings of the International Symposium on Physical Design, pp. 47-54, 2010 ACM International Symposium on Physical Design, ISPD'10, San Francisco, CA, United States, 14/03/10. https://doi.org/10.1145/1735023.1735039

Automatic generation of hierarchical placement rules for analog integrated circuits. / Eick, Michael; Strasser, Martin; Graeb, Helmut E. et al.
ISPD'10 - Proceedings of the 2010 ACM International Symposium on Physical Design. 2010. p. 47-54 (Proceedings of the International Symposium on Physical Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Automatic generation of hierarchical placement rules for analog integrated circuits

AU - Eick, Michael

AU - Strasser, Martin

AU - Graeb, Helmut E.

AU - Schlichtmann, Ulf

PY - 2010

Y1 - 2010

N2 - This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement. The netlist, a library of building blocks and a symmetry analysis are the basis to determine a constraint requirement graph, which comprises five types of proximity, matching and symmetry constraints. According to the priority of the constraint types, a hierarchical partitioning of the circuit into matching, proximity and symmetry groups is then automatically computed and forwarded to a state-of-the-art placement tool. Based on experimental results, we show that the new approach generates more placement rules and leads to better circuit performances according to post-layout simulation compared to a commercial approach.

AB - This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement. The netlist, a library of building blocks and a symmetry analysis are the basis to determine a constraint requirement graph, which comprises five types of proximity, matching and symmetry constraints. According to the priority of the constraint types, a hierarchical partitioning of the circuit into matching, proximity and symmetry groups is then automatically computed and forwarded to a state-of-the-art placement tool. Based on experimental results, we show that the new approach generates more placement rules and leads to better circuit performances according to post-layout simulation compared to a commercial approach.

KW - Analog integrated circuits

KW - Constraints

KW - Hierarchical placement rules

KW - Placement

UR - https://www.scopus.com/pages/publications/77952252494

U2 - 10.1145/1735023.1735039

DO - 10.1145/1735023.1735039

M3 - Conference contribution

AN - SCOPUS:77952252494

SN - 9781605589206

T3 - Proceedings of the International Symposium on Physical Design

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BT - ISPD'10 - Proceedings of the 2010 ACM International Symposium on Physical Design

T2 - 2010 ACM International Symposium on Physical Design, ISPD'10

Y2 - 14 March 2010 through 17 March 2010

ER -

Automatic generation of hierarchical placement rules for analog integrated circuits

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Conference

Keywords

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