Automatic generation of hierarchical placement rules for analog integrated circuits

Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

This paper presents a new method to automatically generate hierarchical placement rules, which are crucial for a successful analog placement. The netlist, a library of building blocks and a symmetry analysis are the basis to determine a constraint requirement graph, which comprises five types of proximity, matching and symmetry constraints. According to the priority of the constraint types, a hierarchical partitioning of the circuit into matching, proximity and symmetry groups is then automatically computed and forwarded to a state-of-the-art placement tool. Based on experimental results, we show that the new approach generates more placement rules and leads to better circuit performances according to post-layout simulation compared to a commercial approach.

Original languageEnglish
Title of host publicationISPD'10 - Proceedings of the 2010 ACM International Symposium on Physical Design
Pages47-54
Number of pages8
DOIs
StatePublished - 2010
Event2010 ACM International Symposium on Physical Design, ISPD'10 - San Francisco, CA, United States
Duration: 14 Mar 201017 Mar 2010

Publication series

NameProceedings of the International Symposium on Physical Design

Conference

Conference2010 ACM International Symposium on Physical Design, ISPD'10
Country/TerritoryUnited States
CitySan Francisco, CA
Period14/03/1017/03/10

Keywords

  • Analog integrated circuits
  • Constraints
  • Hierarchical placement rules
  • Placement

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