Automated Phase-Noise-Aware Design of RF Clock Distribution Circuits

This paper presents a methodology for phase-noise-aware design of RF clock distribution networks. The methodology is embedded within a commercial digital toolchain. It consists of a method for phase noise analysis based on lookup tables, a buffer insertion algorithm providing an optimal buffering for large interconnect trees and a gate sizing algorithm that offers fast power minimization, subject to noise constraints. The phase noise estimate produced by the proposed method on average deviates by less than 3.45% from SPICE simulation results; however, it can be computed three to five orders of magnitude faster. The proposed buffer insertion methodology can easily handle very large industrial examples. It completes within seconds, compared to days for methodologies used in industry today. The gate sizing optimization offers three to four orders of magnitude speedup, compared to commercial products, while producing comparable results. The proposed design methodology reduces the design time of RF clock distribution networks from weeks to a few hours by eliminating the need for manual circuit design, analog simulations, and manual layout. To the extent of our knowledge, this is the first paper on the design automation of RF clock distribution networks.