Automated construction of a cycle-approximate transaction level model of a memory controller

Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

Transaction level (TL) models are key to early design exploration, performance estimation and virtual prototyping. Their speed and accuracy enable early and rapid System-on-Chip (SoC) design evaluation and software development. Most devices have only register transfer level (RTL) models that are too complex for SoC simulation. Abstracting these models to TL ones, however, is a challenging task, especially when the RTL description is too obscure or not accessible. This work presents a methodology for automatically creating a TL model of an RTL memory controller component. The device is treated as a black box and a multitude of simulations is used to obtain results, showing its timing behavior. The results are classified into conditional probability distributions, which are reused within a TL model to approximate the RTL timing behavior. The presented method is very fast and highly accurate. The resulting TL model executes approximately 1200 times faster, with a maximum measured average timing offset error of 7.66%.

Original languageEnglish
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1066-1071
Number of pages6
ISBN (Print)9783981080186
DOIs
StatePublished - 2012
Event15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 - Dresden, Germany
Duration: 12 Mar 201216 Mar 2012

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

Conference15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
Country/TerritoryGermany
CityDresden
Period12/03/1216/03/12

Fingerprint

Dive into the research topics of 'Automated construction of a cycle-approximate transaction level model of a memory controller'. Together they form a unique fingerprint.

Cite this