Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window

Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Duenkel, Steven Soss, Sven Beyer, Rajiv Joshi, Yogesh S. Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations

Abstract

In this work, we applied the asymmetric double-gate concept to decouple the tradeoff between ferroelectric (FE) thickness (tFE) scaling and memory window (MW) reduction in ferroelectric FET (FeFET). We demonstrate that: i) separating read and write gates and adopting a thick non-FE dielectric gate used for reading can amplify the read MW due to electrostatic coupling between the two gates; ii) a compact model for double-gate FeFET has been demonstrated and calibrated with the experimentally measured switching dynamics; iii) with the calibrated model, design space for a scaled tFE (3nm) and logic-compatible write voltage (1.8V) is identified, offering a possible option for tFE scaling.

Original languageEnglish
Title of host publication2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages395-396
Number of pages2
ISBN (Electronic)9781665497725
DOIs
StatePublished - 2022
Externally publishedYes
Event2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States
Duration: 12 Jun 202217 Jun 2022

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2022-June
ISSN (Print)0743-1562

Conference

Conference2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/TerritoryUnited States
CityHonolulu
Period12/06/2217/06/22

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