Area-Efficient Hardware Parallelization of Neural Network CD Equalizers for 4×200 Gb/s PAM4 CWDM4 Systems

Bo Liu; Christian Bluemm; Stefano Calabr`o; Bing Li; Ulf Schlichtmann

doi:10.1049/icp.2023.1893

Area-Efficient Hardware Parallelization of Neural Network CD Equalizers for 4×200 Gb/s PAM4 CWDM4 Systems

Bo Liu
, Christian Bluemm
, Stefano Calabr`o
, Bing Li
, Ulf Schlichtmann

Chair of Electronic Design Automation

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

We compare hardware parallelization of CD equalizers on 10 km 4x200 Gb/s IM/DD PAM4 O-band measurements. A single neural network equalizer with multiple output symbols saves 20% of reference chip area versus multiple single-symbol output variants and 77% versus Volterra non-linear equalizers. Multi-Task learning enables cost-efficient scenario flexibility.

Original language	English
Title of host publication	49th European Conference on Optical Communications, ECOC 2023
Publisher	Institution of Engineering and Technology
Pages	139-142
Number of pages	4
Volume	2023
Edition	34
ISBN (Electronic)	9781839539268
DOIs	https://doi.org/10.1049/icp.2023.1893
State	Published - 2023
Event	49th European Conference on Optical Communications, ECOC 2023 - Hybrid, Glasgow, United Kingdom Duration: 1 Oct 2023 → 5 Oct 2023

Conference

Conference	49th European Conference on Optical Communications, ECOC 2023
Country/Territory	United Kingdom
City	Hybrid, Glasgow
Period	1/10/23 → 5/10/23

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10.1049/icp.2023.1893

Cite this

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title = "Area-Efficient Hardware Parallelization of Neural Network CD Equalizers for 4×200 Gb/s PAM4 CWDM4 Systems",

abstract = "We compare hardware parallelization of CD equalizers on 10 km 4x200 Gb/s IM/DD PAM4 O-band measurements. A single neural network equalizer with multiple output symbols saves 20\% of reference chip area versus multiple single-symbol output variants and 77\% versus Volterra non-linear equalizers. Multi-Task learning enables cost-efficient scenario flexibility.",

author = "Bo Liu and Christian Bluemm and Stefano Calabr`o and Bing Li and Ulf Schlichtmann",

note = "Publisher Copyright: {\textcopyright} The Institution of Engineering \& Technology 2023.; 49th European Conference on Optical Communications, ECOC 2023 ; Conference date: 01-10-2023 Through 05-10-2023",

year = "2023",

doi = "10.1049/icp.2023.1893",

language = "English",

volume = "2023",

pages = "139--142",

booktitle = "49th European Conference on Optical Communications, ECOC 2023",

publisher = "Institution of Engineering and Technology",

edition = "34",

}

Liu, B, Bluemm, C, Calabr`o, S, Li, B & Schlichtmann, U 2023, Area-Efficient Hardware Parallelization of Neural Network CD Equalizers for 4×200 Gb/s PAM4 CWDM4 Systems. in 49th European Conference on Optical Communications, ECOC 2023. 34 edn, vol. 2023, Institution of Engineering and Technology, pp. 139-142, 49th European Conference on Optical Communications, ECOC 2023, Hybrid, Glasgow, United Kingdom, 1/10/23. https://doi.org/10.1049/icp.2023.1893

Area-Efficient Hardware Parallelization of Neural Network CD Equalizers for 4×200 Gb/s PAM4 CWDM4 Systems. / Liu, Bo; Bluemm, Christian; Calabr`o, Stefano et al.
49th European Conference on Optical Communications, ECOC 2023. Vol. 2023 34. ed. Institution of Engineering and Technology, 2023. p. 139-142.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Li, Bing

AU - Schlichtmann, Ulf

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AB - We compare hardware parallelization of CD equalizers on 10 km 4x200 Gb/s IM/DD PAM4 O-band measurements. A single neural network equalizer with multiple output symbols saves 20% of reference chip area versus multiple single-symbol output variants and 77% versus Volterra non-linear equalizers. Multi-Task learning enables cost-efficient scenario flexibility.

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DO - 10.1049/icp.2023.1893

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PB - Institution of Engineering and Technology

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Y2 - 1 October 2023 through 5 October 2023

ER -

Area-Efficient Hardware Parallelization of Neural Network CD Equalizers for 4×200 Gb/s PAM4 CWDM4 Systems

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