TY - GEN
T1 - Architectural vulnerability factor estimation with Backwards Analysis
AU - Hartl, Robert
AU - Rohatschek, Andreas J.
AU - Stechele, Walter
AU - Herkersdorf, Andreas
PY - 2010
Y1 - 2010
N2 - Single-Event-Upsets in synchronous register-based designs are a severe problem for safety-critical applications. Exact and detailed error rate estimations are needed to determine a system's level of reliability. Available methods for estimation consider only special effects, use special reliability models or are computationally intensive. We present an innovative method that is able to calculate the architectural vulnerability factor (AVF) of any RT-level circuit description by applying time-reversed stimulus values. This method, which we call Backwards Analysis, considers all major masking effects (logic masking, information lifetime, timing derating, transitive masking) in a single algorithm and delivers results in several levels of detail from average AVF through sensitivity waveforms. The results show the critical parts and states of a design, which could be used for reliability assessment and selective hardening of the circuit to reach a target failure rate.
AB - Single-Event-Upsets in synchronous register-based designs are a severe problem for safety-critical applications. Exact and detailed error rate estimations are needed to determine a system's level of reliability. Available methods for estimation consider only special effects, use special reliability models or are computationally intensive. We present an innovative method that is able to calculate the architectural vulnerability factor (AVF) of any RT-level circuit description by applying time-reversed stimulus values. This method, which we call Backwards Analysis, considers all major masking effects (logic masking, information lifetime, timing derating, transitive masking) in a single algorithm and delivers results in several levels of detail from average AVF through sensitivity waveforms. The results show the critical parts and states of a design, which could be used for reliability assessment and selective hardening of the circuit to reach a target failure rate.
UR - http://www.scopus.com/inward/record.url?scp=78649807538&partnerID=8YFLogxK
U2 - 10.1109/DSD.2010.104
DO - 10.1109/DSD.2010.104
M3 - Conference contribution
AN - SCOPUS:78649807538
SN - 9780769541716
T3 - Proceedings - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010
SP - 605
EP - 612
BT - Proceedings - 13th Euromicro Conference on Digital System Design
T2 - 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2010
Y2 - 1 September 2010 through 3 September 2010
ER -