Architectural and circuit design techniques for power management of ultra-low-power MCU systems

A holistic power saving concept for ultra-low-power microcontroller (MCU) systems involving application requirements, system architecture, and circuit design techniques is presented. The key of this concept is a digitally enhanced low dropout regulator (LDO) supplying the MCU digital core. By making use of known system power information, the LDO digitally adapts its maximum current drive capability up to 2.56 mA while its quiescent current is as low as 650 nA in light load conditions. In this way, the power management overhead is drastically reduced when operating at low clock speeds enabling system energy savings of 31% at 1 MHz. At the same time, a drastic reduction of the LDO output capacitance enables ultra-low-power consumption during sleep and energy efficient wake-up, resulting in system energy savings up to a factor of 4.6.