Applying GNNs to timing estimation at RTL

Keyphrases

• Register Transfer Level 100%
• Graph Neural Network 100%
• Time Estimation 100%
• Electronic Design Automation 80%
• Training Data 20%
• Recent Advances 20%
• Machine Learning 20%
• Neural Network Model 20%
• Timing Behavior 20%
• Design Flow 20%
• Prediction Task 20%
• Microarchitecture 20%
• Timing Analysis 20%
• Design Metrics 20%
• ASIC Synthesis 20%
• Design Iteration 20%
• Timing Violation 20%
• Edge Feature 20%
• Chip Component 20%
• Initial Design 20%
• Level Design 20%
• Delay-critical 20%
• Node Features 20%
• Physical Synthesis 20%
• Paper Map 20%
• Electronic Design Automation Tools 20%
• Hardware Generation 20%
• Metric Prediction 20%
• Open-source Electronics 20%
• Solution Map 20%
• Unseen 20%
• Generation Framework 20%

Computer Science

• Register-Transfer Level 100%
• Graph Neural Network 100%
• Electronic Design Automation 100%
• Open Source 20%
• Timing Behavior 20%
• Application Specific Integrated Circuit 20%
• Microarchitecture 20%
• Timing Analysis 20%
• Automation Tool 20%
• Critical Delay 20%
• Register-Transfer-Level Implementation 20%
• Training Data 20%
• Design Iteration 20%
• Computer Hardware 20%
• Machine Learning 20%
• Learning System 20%