Analysis of read current and write trip voltage variability from a 1-MB SRAM test structure

Thomas Fischer; Ettore Amirante; Peter Huber; Thomas Nirschl; Alexander Olbrich; Martin Ostermayr; Doris Schmitt-Landsiedel

doi:10.1109/TSM.2008.2004329

Analysis of read current and write trip voltage variability from a 1-MB SRAM test structure

Thomas Fischer
, Ettore Amirante
, Peter Huber
, Thomas Nirschl
, Alexander Olbrich
, Martin Ostermayr
, Doris Schmitt-Landsiedel

Medicine and Health

Research output: Contribution to journal › Article › peer-review

38 Scopus citations

Abstract

We present an area efficient test structure that allows measurement of the statistical distribution of SRAM cell read currents and write trip voltages for 1 million SRAM core cells. The data taken from measurements of wafers fabricated with a 90-nm and 65-nm CMOS process flow show that the device variations are Gaussian distributed for more than 1 million devices, covering more than 5 sigma of variation. The analysis of the measured SRAM performances validate Monte Carlo simulations.

Original language	English
Article number	4657436
Pages (from-to)	534-541
Number of pages	8
Journal	IEEE Transactions on Semiconductor Manufacturing
Volume	21
Issue number	4
DOIs	https://doi.org/10.1109/TSM.2008.2004329
State	Published - Nov 2008

Keywords

65 and 90 nm
Low voltage
Measurement structure
Read current
SRAM
Variation
Write trip voltage

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10.1109/TSM.2008.2004329

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title = "Analysis of read current and write trip voltage variability from a 1-MB SRAM test structure",

abstract = "We present an area efficient test structure that allows measurement of the statistical distribution of SRAM cell read currents and write trip voltages for 1 million SRAM core cells. The data taken from measurements of wafers fabricated with a 90-nm and 65-nm CMOS process flow show that the device variations are Gaussian distributed for more than 1 million devices, covering more than 5 sigma of variation. The analysis of the measured SRAM performances validate Monte Carlo simulations.",

keywords = "65 and 90 nm, Low voltage, Measurement structure, Read current, SRAM, Variation, Write trip voltage",

author = "Thomas Fischer and Ettore Amirante and Peter Huber and Thomas Nirschl and Alexander Olbrich and Martin Ostermayr and Doris Schmitt-Landsiedel",

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AU - Fischer, Thomas

AU - Amirante, Ettore

AU - Huber, Peter

AU - Nirschl, Thomas

AU - Olbrich, Alexander

AU - Ostermayr, Martin

AU - Schmitt-Landsiedel, Doris

PY - 2008/11

Y1 - 2008/11

N2 - We present an area efficient test structure that allows measurement of the statistical distribution of SRAM cell read currents and write trip voltages for 1 million SRAM core cells. The data taken from measurements of wafers fabricated with a 90-nm and 65-nm CMOS process flow show that the device variations are Gaussian distributed for more than 1 million devices, covering more than 5 sigma of variation. The analysis of the measured SRAM performances validate Monte Carlo simulations.

AB - We present an area efficient test structure that allows measurement of the statistical distribution of SRAM cell read currents and write trip voltages for 1 million SRAM core cells. The data taken from measurements of wafers fabricated with a 90-nm and 65-nm CMOS process flow show that the device variations are Gaussian distributed for more than 1 million devices, covering more than 5 sigma of variation. The analysis of the measured SRAM performances validate Monte Carlo simulations.

KW - 65 and 90 nm

KW - Low voltage

KW - Measurement structure

KW - Read current

KW - SRAM

KW - Variation

KW - Write trip voltage

UR - https://www.scopus.com/pages/publications/55649122323

U2 - 10.1109/TSM.2008.2004329

DO - 10.1109/TSM.2008.2004329

M3 - Article

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JO - IEEE Transactions on Semiconductor Manufacturing

JF - IEEE Transactions on Semiconductor Manufacturing

IS - 4

M1 - 4657436

ER -

Analysis of read current and write trip voltage variability from a 1-MB SRAM test structure

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Keywords

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