TY - GEN
T1 - Analog transaction level modeling
AU - Rath, Alexander W.
AU - Esen, Volkan
AU - Ecker, Wolfgang
PY - 2011
Y1 - 2011
N2 - Due to the better technology scaling of digital blocks compared to analog blocks, more and more parts of the analog implementation of modern IC designs are shifted to the digital domain, leading to mixed signal designs. However, no verification methodology, that considers the functional verification task of digital and analog blocks holistically, exists so far, whereas many verification methodologies for the digital domain have arisen over time; the newest being the Universal Verification Methodology (UVM) standard [1].
AB - Due to the better technology scaling of digital blocks compared to analog blocks, more and more parts of the analog implementation of modern IC designs are shifted to the digital domain, leading to mixed signal designs. However, no verification methodology, that considers the functional verification task of digital and analog blocks holistically, exists so far, whereas many verification methodologies for the digital domain have arisen over time; the newest being the Universal Verification Methodology (UVM) standard [1].
UR - https://www.scopus.com/pages/publications/84856171343
U2 - 10.1109/HLDVT.2011.6114171
DO - 10.1109/HLDVT.2011.6114171
M3 - Conference contribution
AN - SCOPUS:84856171343
SN - 9781457717444
T3 - Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
SP - 82
BT - 2011 IEEE International High Level Design Validation and Test Workshop, HLDVT'11
T2 - 16th IEEE International High Level Design Validation and Test Workshop, HLDVT'11
Y2 - 10 November 2011 through 11 November 2011
ER -