Analog fault simulation automation at schematic level with random sampling techniques

Liang Wu, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Muller, Christoph Scheytt, Wolfgang Ecker

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation.

Original languageEnglish
Title of host publicationProceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538652916
DOIs
StatePublished - 29 May 2018
Externally publishedYes
Event13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018 - Taormina, Italy
Duration: 10 Apr 201812 Apr 2018

Publication series

NameProceedings - 2018 13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018

Conference

Conference13th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2018
Country/TerritoryItaly
CityTaormina
Period10/04/1812/04/18

Keywords

  • analog fault
  • defect model
  • fault coverage
  • fault injection
  • fault model
  • fault probability
  • fault simulation
  • sampling technique

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