An Si schottky diode demultiplexer circuit for high bit-rate optical receivers

Jung Han Choi; Gerhard R. Olbrich; Peter Russer

doi:10.1109/TMTT.2005.848820

An Si schottky diode demultiplexer circuit for high bit-rate optical receivers

Jung Han Choi, Gerhard R. Olbrich, Peter Russer

Technical University of Munich

Technical University of Munich

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

We demonstrate an Si Schottky diode sampling demultiplexer circuit for an optical receiver. A system model and the operation principle of the sampling demultiplexer are described. The Si Schottky diode sampling circuit has been realized in conductor-backed coplanar waveguide technology and fabricated in thin-film technology. The sampling circuit module was measured using a 43-Gb/s nonreturn-to-zero signal. In addition, for the purpose of reducing the intersymbol interference, a linear tapped delay-line equalizer circuit has been designed and simulated. The weight of the taps has been calculated employing a zero-forcing algorithm.

Original language	English
Pages (from-to)	2033-2041
Number of pages	9
Journal	IEEE Transactions on Microwave Theory and Techniques
Volume	53
Issue number	6 II
DOIs	https://doi.org/10.1109/TMTT.2005.848820
State	Published - Jun 2005

Keywords

160 Gb/s
80 Gb/s
Coplanar waveguide (CPW)
Demultiplexer
Flip-chip
Intersymbol interference (LSI)
Linear equalizer
Optical receiver
Root-diode model
Sampling
Si Schottky diode

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10.1109/TMTT.2005.848820

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@article{722a4297120e441fbf484daf6411b1d3,

title = "An Si schottky diode demultiplexer circuit for high bit-rate optical receivers",

abstract = "We demonstrate an Si Schottky diode sampling demultiplexer circuit for an optical receiver. A system model and the operation principle of the sampling demultiplexer are described. The Si Schottky diode sampling circuit has been realized in conductor-backed coplanar waveguide technology and fabricated in thin-film technology. The sampling circuit module was measured using a 43-Gb/s nonreturn-to-zero signal. In addition, for the purpose of reducing the intersymbol interference, a linear tapped delay-line equalizer circuit has been designed and simulated. The weight of the taps has been calculated employing a zero-forcing algorithm.",

keywords = "160 Gb/s, 80 Gb/s, Coplanar waveguide (CPW), Demultiplexer, Flip-chip, Intersymbol interference (LSI), Linear equalizer, Optical receiver, Root-diode model, Sampling, Si Schottky diode",

author = "Choi, {Jung Han} and Olbrich, {Gerhard R.} and Peter Russer",

note = "Funding Information: Manuscript received October 1, 2004; revised February 23, 2005. This work was supported by Siemens AG and by the Bundesministerium f{\"u}r Bildung und Forschung under Contract 01 BP 156. The authors are with the Institute for High-Frequency Engineering, Technische Universit{\"a}t M{\"u}nchen, 80333 Munich, Germany (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2005.848820",

year = "2005",

month = jun,

doi = "10.1109/TMTT.2005.848820",

language = "English",

volume = "53",

pages = "2033--2041",

journal = "IEEE Transactions on Microwave Theory and Techniques",

issn = "0018-9480",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6 II",

}

TY - JOUR

T1 - An Si schottky diode demultiplexer circuit for high bit-rate optical receivers

AU - Choi, Jung Han

AU - Olbrich, Gerhard R.

AU - Russer, Peter

N1 - Funding Information: Manuscript received October 1, 2004; revised February 23, 2005. This work was supported by Siemens AG and by the Bundesministerium für Bildung und Forschung under Contract 01 BP 156. The authors are with the Institute for High-Frequency Engineering, Technische Universität München, 80333 Munich, Germany (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TMTT.2005.848820

PY - 2005/6

Y1 - 2005/6

N2 - We demonstrate an Si Schottky diode sampling demultiplexer circuit for an optical receiver. A system model and the operation principle of the sampling demultiplexer are described. The Si Schottky diode sampling circuit has been realized in conductor-backed coplanar waveguide technology and fabricated in thin-film technology. The sampling circuit module was measured using a 43-Gb/s nonreturn-to-zero signal. In addition, for the purpose of reducing the intersymbol interference, a linear tapped delay-line equalizer circuit has been designed and simulated. The weight of the taps has been calculated employing a zero-forcing algorithm.

AB - We demonstrate an Si Schottky diode sampling demultiplexer circuit for an optical receiver. A system model and the operation principle of the sampling demultiplexer are described. The Si Schottky diode sampling circuit has been realized in conductor-backed coplanar waveguide technology and fabricated in thin-film technology. The sampling circuit module was measured using a 43-Gb/s nonreturn-to-zero signal. In addition, for the purpose of reducing the intersymbol interference, a linear tapped delay-line equalizer circuit has been designed and simulated. The weight of the taps has been calculated employing a zero-forcing algorithm.

KW - 160 Gb/s

KW - 80 Gb/s

KW - Coplanar waveguide (CPW)

KW - Demultiplexer

KW - Flip-chip

KW - Intersymbol interference (LSI)

KW - Linear equalizer

KW - Optical receiver

KW - Root-diode model

KW - Sampling

KW - Si Schottky diode

UR - http://www.scopus.com/inward/record.url?scp=23144446727&partnerID=8YFLogxK

U2 - 10.1109/TMTT.2005.848820

DO - 10.1109/TMTT.2005.848820

M3 - Article

AN - SCOPUS:23144446727

SN - 0018-9480

VL - 53

SP - 2033

EP - 2041

JO - IEEE Transactions on Microwave Theory and Techniques

JF - IEEE Transactions on Microwave Theory and Techniques

IS - 6 II

ER -

An Si schottky diode demultiplexer circuit for high bit-rate optical receivers

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Keywords

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