An interface algebra for estimating worst-case traversal times in component networks

Nikolay Stoimenov, Samarjit Chakraborty, Lothar Thiele

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Interface-based design relies on the idea that different components of a system may be developed independently and a system designer can connect them together only if their interfaces match, without knowing the details of their internals. In this paper we propose an interface algebra for analyzing networks of embedded systems components. The goal is to be able to compute worst-case traversal times and verify their compliance to provided deadlines in such component networks in an incremental manner, i.e., as and when new components are added or removed from the network. We lay the basic groundwork for this algebra and show its utility through an illustrative example.

Original languageEnglish
Title of host publicationLeveraging Applications of Formal Methods, Verification, and Validation - 4th International Symposium on Leveraging Applications, ISoLA 2010, Proceedings
Pages198-213
Number of pages16
EditionPART 1
DOIs
StatePublished - 2010
Event4th International Symposium on Leveraging Applications, ISoLA 2010 - Heraklion, Crete, Greece
Duration: 18 Oct 201021 Oct 2010

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
NumberPART 1
Volume6415 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference4th International Symposium on Leveraging Applications, ISoLA 2010
Country/TerritoryGreece
CityHeraklion, Crete
Period18/10/1021/10/10

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