TY - GEN
T1 - An FPGA-Accelerated Atom Sorting Unit for Neutral Atom Quantum Computers
AU - Guo, Xiaorang
AU - Winklmann, Jonas
AU - Stober, Dirk
AU - Cao, Shicong
AU - Schulz, Martin
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Neutral atoms have been proven to be a promising physical platform for quantum computing because of their longer coherence time and good scalability. To operate neutral-atom quantum computers, an essential step before computation is to assemble the atoms as a defect-free array. This process is called atom rearrangement or atom sorting, which typically requires a long analysis time on classical computers. To optimize the sorting process, we propose a hardware-friendly sorting algorithm (oriented for FPGA acceleration) to be able to analyze the atom array with four independent quadrants and process each quadrant in parallel. Tested on a Xilinx ZCU216 FPGA, our design can finish the sorting analysis procedure with a 50 ×50 loaded atoms array with around 1.0 μs. Compared to the CPU implementation, we achieved an acceleration of around 50× speedup in algorithm analysis time. In addition, the design exhibits good scalability in execution time, making it suitable for large-scale quantum systems.
AB - Neutral atoms have been proven to be a promising physical platform for quantum computing because of their longer coherence time and good scalability. To operate neutral-atom quantum computers, an essential step before computation is to assemble the atoms as a defect-free array. This process is called atom rearrangement or atom sorting, which typically requires a long analysis time on classical computers. To optimize the sorting process, we propose a hardware-friendly sorting algorithm (oriented for FPGA acceleration) to be able to analyze the atom array with four independent quadrants and process each quadrant in parallel. Tested on a Xilinx ZCU216 FPGA, our design can finish the sorting analysis procedure with a 50 ×50 loaded atoms array with around 1.0 μs. Compared to the CPU implementation, we achieved an acceleration of around 50× speedup in algorithm analysis time. In addition, the design exhibits good scalability in execution time, making it suitable for large-scale quantum systems.
UR - http://www.scopus.com/inward/record.url?scp=85217153526&partnerID=8YFLogxK
U2 - 10.1109/QCE60285.2024.10399
DO - 10.1109/QCE60285.2024.10399
M3 - Conference contribution
AN - SCOPUS:85217153526
T3 - Proceedings - IEEE Quantum Week 2024, QCE 2024
SP - 549
EP - 550
BT - Workshops Program, Posters Program, Panels Program and Tutorials Program
A2 - Culhane, Candace
A2 - Byrd, Greg T.
A2 - Muller, Hausi
A2 - Alexeev, Yuri
A2 - Alexeev, Yuri
A2 - Sheldon, Sarah
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th IEEE International Conference on Quantum Computing and Engineering, QCE 2024
Y2 - 15 September 2024 through 20 September 2024
ER -