TY - GEN
T1 - An efficient hardware architecture for packet re-sequencing in network processors MPSoCs
AU - Traboulsi, Shadi
AU - Meitinger, Michael
AU - Ohlendorf, Rainer
AU - Herkersdorf, Andreas
PY - 2009
Y1 - 2009
N2 - Due to the multi-processor nature of Network Processors (NP), data packets entering the system are processed in parallel and might be transmitted out-of-order at the output leading to a significant degradation in network performance. In this paper we propose a new well-structured, area-efficient, and high speed hardware architecture for packet re-sequencing. For this purpose, several buffering techniques were investigated and analyzed in terms of complexity and memory requirements, taking into consideration the networking application and the impact of the number of processing elements (PE) on packet reordering. The proposed architecture, based on the appropriate buffering mechanism, is then demonstrated and implemented on our FPGA-based prototyping platform. In contrast to other solutions, our results showed 80% more efficient resource utilization while being capable to achieve 10% higher data rate of 3.2 Gbit/s.
AB - Due to the multi-processor nature of Network Processors (NP), data packets entering the system are processed in parallel and might be transmitted out-of-order at the output leading to a significant degradation in network performance. In this paper we propose a new well-structured, area-efficient, and high speed hardware architecture for packet re-sequencing. For this purpose, several buffering techniques were investigated and analyzed in terms of complexity and memory requirements, taking into consideration the networking application and the impact of the number of processing elements (PE) on packet reordering. The proposed architecture, based on the appropriate buffering mechanism, is then demonstrated and implemented on our FPGA-based prototyping platform. In contrast to other solutions, our results showed 80% more efficient resource utilization while being capable to achieve 10% higher data rate of 3.2 Gbit/s.
KW - Hardware architecture
KW - Multi-processor system-on-chip
KW - Network processors
KW - Packet reordering
UR - http://www.scopus.com/inward/record.url?scp=74549179626&partnerID=8YFLogxK
U2 - 10.1109/DSD.2009.194
DO - 10.1109/DSD.2009.194
M3 - Conference contribution
AN - SCOPUS:74549179626
SN - 9780769537825
T3 - 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009
SP - 11
EP - 18
BT - 12th Euromicro Conference on Digital System Design
T2 - 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009
Y2 - 27 August 2009 through 29 August 2009
ER -