An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs

The trend toward scaling and more complex fabrication techniques in digital circuit design often leads to numerous faults within Integrated Circuits (ICs). To address these vulnerabilities, various Design-for-Test (DFT) techniques have been developed for thorough testing during IC manufacturing. However, integrating these DFT infrastructures introduces significant overhead in both area and performance. To overcome these challenges, especially for testing processor cores, Software-Based Self Test (SBST) has emerged as a promising alternative. This paper proposes a novel, automated, and efficient approach for generating SBST tailored for RISC-V processor cores. By combining formal verification with fault simulation, the number of required assertions is reduced by eliminating faults detected by existing test patterns. In addition to SBST generation, our approach introduces a novel Program Flow Checking (PFC) technique, ensuring adherence to ISO 26262 standards and providing a high Fault Detection Rate (FDR). Experimental results show that various RISC-V processor components achieve Fault Coverage (FC) greater than 91%, with the PFC providing a 100% FDR for most components. The methodology is fully automated, utilizing Model-Driven Architecture (MDA) principles.