An architecture for runtime evaluation of SoC reliability

Andreas Bernauer; Oliver Bringmann; Wolfgang Rosenstiel; Abdelmajid Bouajila; Walter Stechele; Andreas Herkersdorf

An architecture for runtime evaluation of SoC reliability

Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

This paper presents an architecture to evaluate the reliability of a system-on-chip (SoC) during its runtime that also accounts for the system's redundancy. We propose to integrate an autonomic layer into the SoC to detect the chip's current condition and instruct appropriate countermeasures. In the autonomic layer, error counters are used to count the number of errors within a fixed time interval. The counters' values accumulate into a global register representing the system's reliability. The accumulation takes into account the series and parallel composition of the system.

Original language	English
Title of host publication	INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI)
Pages	177-184
Number of pages	8
State	Published - 2006
Externally published	Yes
Event	36th Jahrestagung der Gesellschaft fur Informatik e.V. (GI): Informatik fur Menschen, INFORMATIK 2006 36th Annual Conference of the German Informatics Society (GI): Informatics for People, INFORMATIK 2006 - Dresden, Germany Duration: 2 Oct 2006 → 6 Oct 2006

Publication series

Name	INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI)
Volume	1

Conference

Conference	36th Jahrestagung der Gesellschaft fur Informatik e.V. (GI): Informatik fur Menschen, INFORMATIK 2006 36th Annual Conference of the German Informatics Society (GI): Informatics for People, INFORMATIK 2006
Country/Territory	Germany
City	Dresden
Period	2/10/06 → 6/10/06

Cite this

Bernauer, A., Bringmann, O., Rosenstiel, W., Bouajila, A., Stechele, W., & Herkersdorf, A. (2006). An architecture for runtime evaluation of SoC reliability. In INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI) (pp. 177-184). (INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI); Vol. 1).

Bernauer, Andreas ; Bringmann, Oliver ; Rosenstiel, Wolfgang et al. / An architecture for runtime evaluation of SoC reliability. INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI). 2006. pp. 177-184 (INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI)).

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title = "An architecture for runtime evaluation of SoC reliability",

abstract = "This paper presents an architecture to evaluate the reliability of a system-on-chip (SoC) during its runtime that also accounts for the system's redundancy. We propose to integrate an autonomic layer into the SoC to detect the chip's current condition and instruct appropriate countermeasures. In the autonomic layer, error counters are used to count the number of errors within a fixed time interval. The counters' values accumulate into a global register representing the system's reliability. The accumulation takes into account the series and parallel composition of the system.",

author = "Andreas Bernauer and Oliver Bringmann and Wolfgang Rosenstiel and Abdelmajid Bouajila and Walter Stechele and Andreas Herkersdorf",

year = "2006",

language = "English",

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series = "INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI)",

pages = "177--184",

booktitle = "INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI)",

note = "36th Jahrestagung der Gesellschaft fur Informatik e.V. (GI): Informatik fur Menschen, INFORMATIK 2006 36th Annual Conference of the German Informatics Society (GI): Informatics for People, INFORMATIK 2006 ; Conference date: 02-10-2006 Through 06-10-2006",

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Bernauer, A, Bringmann, O, Rosenstiel, W, Bouajila, A, Stechele, W & Herkersdorf, A 2006, An architecture for runtime evaluation of SoC reliability. in INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI). INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI), vol. 1, pp. 177-184, 36th Jahrestagung der Gesellschaft fur Informatik e.V. (GI): Informatik fur Menschen, INFORMATIK 2006 36th Annual Conference of the German Informatics Society (GI): Informatics for People, INFORMATIK 2006, Dresden, Germany, 2/10/06.

An architecture for runtime evaluation of SoC reliability. / Bernauer, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang et al.
INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI). 2006. p. 177-184 (INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI); Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Stechele, Walter

AU - Herkersdorf, Andreas

PY - 2006

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N2 - This paper presents an architecture to evaluate the reliability of a system-on-chip (SoC) during its runtime that also accounts for the system's redundancy. We propose to integrate an autonomic layer into the SoC to detect the chip's current condition and instruct appropriate countermeasures. In the autonomic layer, error counters are used to count the number of errors within a fixed time interval. The counters' values accumulate into a global register representing the system's reliability. The accumulation takes into account the series and parallel composition of the system.

AB - This paper presents an architecture to evaluate the reliability of a system-on-chip (SoC) during its runtime that also accounts for the system's redundancy. We propose to integrate an autonomic layer into the SoC to detect the chip's current condition and instruct appropriate countermeasures. In the autonomic layer, error counters are used to count the number of errors within a fixed time interval. The counters' values accumulate into a global register representing the system's reliability. The accumulation takes into account the series and parallel composition of the system.

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M3 - Conference contribution

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T2 - 36th Jahrestagung der Gesellschaft fur Informatik e.V. (GI): Informatik fur Menschen, INFORMATIK 2006 36th Annual Conference of the German Informatics Society (GI): Informatics for People, INFORMATIK 2006

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Bernauer A, Bringmann O, Rosenstiel W, Bouajila A, Stechele W , Herkersdorf A. An architecture for runtime evaluation of SoC reliability. In INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI). 2006. p. 177-184. (INFORMATIK 2006 - Informatik fur Menschen, Beitrage der 36. Jahrestagung der Gesellschaft fur Informatik e.V. (GI)).

An architecture for runtime evaluation of SoC reliability

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