An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors

Keyphrases

• Soft Error 100%
• Timing Error 100%
• FPGA Prototype 100%
• Processor Pipeline 100%
• Performance Overhead 50%
• Pipelined Architecture 50%
• Injection Rate 25%
• Low Performance 25%
• Fault Injection 25%
• Error Injection 25%
• Resilient 25%
• LEON3 25%
• Randomly Occurring Faults 25%

Computer Science

• Pipeline Architecture 100%
• Pipeline Processor 100%
• Field Programmable Gate Arrays 100%
• Open Source 50%
• Lower Performance 50%
• Fault Injection 50%
• Error Injection 50%
• Channel Pattern Integration 50%
• Injection Rate 50%