An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors

Abdelmajid Bouajila; Johannes Zeppenfeld; Walter Stechele; Andreas Herkersdorf

doi:10.1109/DDECS.2011.5783084

An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors

Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf

Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

This paper presents a reliable processor pipeline architecture resilient to multiple soft- and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor pipeline has low performance overheads (relative CPI of 1.06 at an error injection rate of 3 %) and is therefore much better than techniques based on flushing.

Original language	English
Title of host publication	Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011
Pages	225-230
Number of pages	6
DOIs	https://doi.org/10.1109/DDECS.2011.5783084
State	Published - 2011
Event	14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011 - Cottbus, Germany Duration: 13 Apr 2011 → 15 Apr 2011

Publication series

Name	Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011

Conference

Conference	14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011
Country/Territory	Germany
City	Cottbus
Period	13/04/11 → 15/04/11

Access to Document

10.1109/DDECS.2011.5783084

Cite this

Bouajila, A., Zeppenfeld, J., Stechele, W., & Herkersdorf, A. (2011). An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. In Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011 (pp. 225-230). Article 5783084 (Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011). https://doi.org/10.1109/DDECS.2011.5783084

Bouajila, Abdelmajid ; Zeppenfeld, Johannes ; Stechele, Walter et al. / An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011. 2011. pp. 225-230 (Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011).

@inproceedings{56753d8f62c946c39e20a65cc48904a4,

title = "An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors",

abstract = "This paper presents a reliable processor pipeline architecture resilient to multiple soft- and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor pipeline has low performance overheads (relative CPI of 1.06 at an error injection rate of 3 %) and is therefore much better than techniques based on flushing.",

author = "Abdelmajid Bouajila and Johannes Zeppenfeld and Walter Stechele and Andreas Herkersdorf",

year = "2011",

doi = "10.1109/DDECS.2011.5783084",

language = "English",

isbn = "9781424497560",

series = "Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011",

pages = "225--230",

booktitle = "Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011",

note = "14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011 ; Conference date: 13-04-2011 Through 15-04-2011",

}

Bouajila, A, Zeppenfeld, J, Stechele, W & Herkersdorf, A 2011, An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. in Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011., 5783084, Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011, pp. 225-230, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011, Cottbus, Germany, 13/04/11. https://doi.org/10.1109/DDECS.2011.5783084

An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. / Bouajila, Abdelmajid; Zeppenfeld, Johannes; Stechele, Walter et al.
Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011. 2011. p. 225-230 5783084 (Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors

AU - Bouajila, Abdelmajid

AU - Zeppenfeld, Johannes

AU - Stechele, Walter

AU - Herkersdorf, Andreas

PY - 2011

Y1 - 2011

N2 - This paper presents a reliable processor pipeline architecture resilient to multiple soft- and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor pipeline has low performance overheads (relative CPI of 1.06 at an error injection rate of 3 %) and is therefore much better than techniques based on flushing.

AB - This paper presents a reliable processor pipeline architecture resilient to multiple soft- and timing errors. It also presents a probabilistic quantification of its performance overheads. This reliable processor pipeline architecture has been implemented in the Leon3 VHDL open source processor. An FPGA prototype running under random fault injection has also been developed. This reliable processor pipeline has low performance overheads (relative CPI of 1.06 at an error injection rate of 3 %) and is therefore much better than techniques based on flushing.

UR - http://www.scopus.com/inward/record.url?scp=79959918533&partnerID=8YFLogxK

U2 - 10.1109/DDECS.2011.5783084

DO - 10.1109/DDECS.2011.5783084

M3 - Conference contribution

AN - SCOPUS:79959918533

SN - 9781424497560

T3 - Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011

SP - 225

EP - 230

BT - Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011

T2 - 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011

Y2 - 13 April 2011 through 15 April 2011

ER -

Bouajila A, Zeppenfeld J, Stechele W , Herkersdorf A. An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. In Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011. 2011. p. 225-230. 5783084. (Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011). doi: 10.1109/DDECS.2011.5783084

An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors

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