An analog perspective on device reliability in 32nm high-k metal gate technology

Florian Raoul Chouard; Shailesh More; Michael Fulde; Doris Schmitt-Landsiedel

doi:10.1109/DDECS.2011.5783049

An analog perspective on device reliability in 32nm high-k metal gate technology

Florian Raoul Chouard, Shailesh More, Michael Fulde, Doris Schmitt-Landsiedel

Medicine and Health

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

An assessment on analog circuit reliability for an advanced 32nm high-k metal gate technology is given from the analog designer's point of view. Selected analog circuit blocks are investigated with respect to device stress states. A custom test structure, designed to reveal analog related device characteristics including relaxation effects, was used to perform stress measurements. In addition to common aging in inversion mode, degradation in accumulation mode is determined. Experiments reveal that relaxation shows a large variety in drift behavior, and degradation induced variations - even for analog size devices - can reach significant values. Both topics are main issues for analog circuits design. Thereupon a general approach to consider device aging for analog circuit reliability is proposed.

Original language	English
Title of host publication	Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011
Pages	65-70
Number of pages	6
DOIs	https://doi.org/10.1109/DDECS.2011.5783049
State	Published - 2011
Event	14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011 - Cottbus, Germany Duration: 13 Apr 2011 → 15 Apr 2011

Publication series

Name	Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011

Conference

Conference	14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011
Country/Territory	Germany
City	Cottbus
Period	13/04/11 → 15/04/11

Keywords

NBTI
PBTI
aging
analog
circuit reliability
degradation

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10.1109/DDECS.2011.5783049

Cite this

Chouard, F. R., More, S., Fulde, M., & Schmitt-Landsiedel, D. (2011). An analog perspective on device reliability in 32nm high-k metal gate technology. In Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011 (pp. 65-70). Article 5783049 (Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011). https://doi.org/10.1109/DDECS.2011.5783049

Chouard, Florian Raoul ; More, Shailesh ; Fulde, Michael et al. / An analog perspective on device reliability in 32nm high-k metal gate technology. Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011. 2011. pp. 65-70 (Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011).

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abstract = "An assessment on analog circuit reliability for an advanced 32nm high-k metal gate technology is given from the analog designer's point of view. Selected analog circuit blocks are investigated with respect to device stress states. A custom test structure, designed to reveal analog related device characteristics including relaxation effects, was used to perform stress measurements. In addition to common aging in inversion mode, degradation in accumulation mode is determined. Experiments reveal that relaxation shows a large variety in drift behavior, and degradation induced variations - even for analog size devices - can reach significant values. Both topics are main issues for analog circuits design. Thereupon a general approach to consider device aging for analog circuit reliability is proposed.",

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author = "Chouard, \{Florian Raoul\} and Shailesh More and Michael Fulde and Doris Schmitt-Landsiedel",

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booktitle = "Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011",

note = "14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011 ; Conference date: 13-04-2011 Through 15-04-2011",

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Chouard, FR, More, S, Fulde, M & Schmitt-Landsiedel, D 2011, An analog perspective on device reliability in 32nm high-k metal gate technology. in Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011., 5783049, Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011, pp. 65-70, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011, Cottbus, Germany, 13/04/11. https://doi.org/10.1109/DDECS.2011.5783049

An analog perspective on device reliability in 32nm high-k metal gate technology. / Chouard, Florian Raoul; More, Shailesh; Fulde, Michael et al.
Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011. 2011. p. 65-70 5783049 (Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Chouard FR, More S, Fulde M, Schmitt-Landsiedel D. An analog perspective on device reliability in 32nm high-k metal gate technology. In Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011. 2011. p. 65-70. 5783049. (Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011). doi: 10.1109/DDECS.2011.5783049

An analog perspective on device reliability in 32nm high-k metal gate technology

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