Abstract
In this paper, a space vector PWM method for three-level inverters is presented. In the proposed technique, boundary restrictions can be easily incorporated to minimize the harmonic distortion output voltages, to limit the minimum pulse width and to balance the voltages of the dc-link capacitor bank. The solutions obtained are simple algebraic equations relating directly the pulse widths of the gate signals to the phase reference voltages. Computer simulation and experimental results are used to demonstrate the main features of the proposed technique.
| Original language | English |
|---|---|
| Pages (from-to) | 2177-2184 |
| Number of pages | 8 |
| Journal | Conference Record - IAS Annual Meeting (IEEE Industry Applications Society) |
| Volume | 4 |
| State | Published - 2000 |
| Externally published | Yes |
| Event | 35th IAS Annual Meeting and World Conference on Industrial Applications of Electrical Energy - Rome, Italy Duration: 8 Oct 2000 → 12 Oct 2000 |