Aging-constrained performance optimization for multi cores

Circuit aging has become a dire design concern and hence it is considered a primary design constraint. Current practice to cope with this problem is to apply (too) conservative means. In contrast, we introduce a far less restrictive approach by efficiently exploring a fundamentally new aging-aware design space comprising temperature (T ), aging degradation (ÄVth) and supply voltage (Vdd ). On that basis, we present a tailored multi core resource management (with # threads and v/f levels as parameters etc.) that aims to maximize performance (optimization goal) under aging constraint(s). We demonstrate that our approach is the first to fully exploit the performance/aging trade-off within this new design space but without the restrictions inherent to current state of the art. As a result, we achieve 43% increase in performance while maintaining the same level of circuit aging when compared to the best technique reported yet.