Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level

Dominik Lorenz; Georg Georgakos; Ulf Schlichtmann

doi:10.1524/itit.2010.0589

Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level

Translated title of the contribution: Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level

Dominik Lorenz
, Georg Georgakos
, Ulf Schlichtmann

Chair of Electronic Design Automation

Technical University of Munich
Infineon Technologies AG

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

The presented aging analysis flow is able to calculate the degraded circuit timing on gate level. It is the first approach considering the impact of the two dominant drift-related aging effects-NBTI and HCI. Our proposed aging-aware gate model, AgeGate, is very accurate. It provides the degraded output slope in addition to the degraded gate delay, and it calculates individual parameter degradations for all transistors of a logic gate.

Translated title of the contribution	Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level
Original language	English
Pages (from-to)	181-187
Number of pages	7
Journal	IT - Information Technology
Volume	52
Issue number	4
DOIs	https://doi.org/10.1524/itit.2010.0589
State	Published - Aug 2010

Keywords

Performance Analysis and Design Aids
aging analysis
gate level

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10.1524/itit.2010.0589

Cite this

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abstract = "The presented aging analysis flow is able to calculate the degraded circuit timing on gate level. It is the first approach considering the impact of the two dominant drift-related aging effects-NBTI and HCI. Our proposed aging-aware gate model, AgeGate, is very accurate. It provides the degraded output slope in addition to the degraded gate delay, and it calculates individual parameter degradations for all transistors of a logic gate.",

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AU - Georgakos, Georg

AU - Schlichtmann, Ulf

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N2 - The presented aging analysis flow is able to calculate the degraded circuit timing on gate level. It is the first approach considering the impact of the two dominant drift-related aging effects-NBTI and HCI. Our proposed aging-aware gate model, AgeGate, is very accurate. It provides the degraded output slope in addition to the degraded gate delay, and it calculates individual parameter degradations for all transistors of a logic gate.

AB - The presented aging analysis flow is able to calculate the degraded circuit timing on gate level. It is the first approach considering the impact of the two dominant drift-related aging effects-NBTI and HCI. Our proposed aging-aware gate model, AgeGate, is very accurate. It provides the degraded output slope in addition to the degraded gate delay, and it calculates individual parameter degradations for all transistors of a logic gate.

KW - Performance Analysis and Design Aids

KW - aging analysis

KW - gate level

UR - https://www.scopus.com/pages/publications/84933551478

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Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level

Abstract

Keywords

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