Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level

Translated title of the contribution: Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level

Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

The presented aging analysis flow is able to calculate the degraded circuit timing on gate level. It is the first approach considering the impact of the two dominant drift-related aging effects-NBTI and HCI. Our proposed aging-aware gate model, AgeGate, is very accurate. It provides the degraded output slope in addition to the degraded gate delay, and it calculates individual parameter degradations for all transistors of a logic gate.

Translated title of the contributionAging-aware Timing Analysis of Combinatorial Circuits on Gate Level
Original languageEnglish
Pages (from-to)181-187
Number of pages7
JournalIT - Information Technology
Volume52
Issue number4
DOIs
StatePublished - Aug 2010

Keywords

  • Performance Analysis and Design Aids
  • aging analysis
  • gate level

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