TY - GEN
T1 - Aging analysis of circuit timing considering NBTI and HCI
AU - Lorenz, Dominik
AU - Georgakos, Georg
AU - Schlichtmann, Ulf
PY - 2009
Y1 - 2009
N2 - We present an aging analysis flow able to calculate the degraded circuit timing. To the best of our knowledge it is the first approach on gate level so far capable of analyzing the impact of the two dominant drift-related aging effects - NBTI and HCI - on complex digital circuits. The aging-aware gate model used to compute the aged circuit timing provides not just the cell delay degradation, but also the degradation of the output slope. To get more accurate results, the individual workload of a gate can be considered.
AB - We present an aging analysis flow able to calculate the degraded circuit timing. To the best of our knowledge it is the first approach on gate level so far capable of analyzing the impact of the two dominant drift-related aging effects - NBTI and HCI - on complex digital circuits. The aging-aware gate model used to compute the aged circuit timing provides not just the cell delay degradation, but also the degradation of the output slope. To get more accurate results, the individual workload of a gate can be considered.
UR - https://www.scopus.com/pages/publications/70449424330
U2 - 10.1109/IOLTS.2009.5195975
DO - 10.1109/IOLTS.2009.5195975
M3 - Conference contribution
AN - SCOPUS:70449424330
SN - 9781424445950
T3 - 2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009
SP - 3
EP - 8
BT - 2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009
T2 - 2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009
Y2 - 24 June 2009 through 26 June 2009
ER -