Advanced packet segmentation and buffering algorithms in network processors

Memory subsystem performance is rapidly becoming an important bottleneck in network processing, partially because packets must be segmented to prevent memory fragmentation. Depending on segment length, accesses to memory are short and thus inefficient or long and hence storing efficiency drops. Besides, segments have one-to-one associated descriptors which require a large control buffer and high management effort to update them. Our contribution consists in allowing multiple segment lengths for packet segmentation even for a single packet. We propose two new segmentation algorithms that ensure a minimum number of segments, so as to achieve maximum packet throughput, while maintaining a high level of memory efficiency together with reducing the amount of control resources needed. Both algorithms are evaluated using a variety of packet traces and realistic system configurations in order to determine how different choices impact the performance and the storage efficiency. The findings were then used to realize the SmartMem Buffer Manager in VHDL, which was tested in a Virtex-4 FPGA and its performance measured to verify the simulation results and validate the higher performance of the proposed algorithms.