Adiabatic 4-bit adders: Comparison of performance and robustness against technology parameter variations

A large number of adiabatic families has been proposed, but there exist only few partial comparisons and no methodical investigations of the robustness of such circuits. Using a 4-bit adder as a reference circuit we compare different adiabatic logic families with respect to energy consumption, area occupation and frequency range. Significant differences among various adiabatic implementations are found and a reduction of energy dissipation compared to standard CMOS up to 200MHz. Energy saving by a typical factor of 10 can be achieved. The effect of supply voltage scaling is investigated as well as the sensitivity to technological parameters. It is shown that different effects due to inter-die and intra-die variations of the threshold voltage can strongly affect the performance of adiabatic circuits, increasing the energy dissipation by 7.7%.