Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit

Martin Wirnshofer; Leonhard Heiß; Anil Narayan Kakade; Nasim Pour Aryan; Georg Georgakos; Doris Schmitt-Landsiedel

doi:10.1109/DDECS.2012.6219058

Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit

Martin Wirnshofer
, Leonhard Heiß
, Anil Narayan Kakade
, Nasim Pour Aryan
, Georg Georgakos
, Doris Schmitt-Landsiedel

Medicine and Health

Technical University of Munich
Infineon Technologies AG

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

The proposed voltage scheme adaptively tunes the supply voltage of digital circuits, according to PVTA variations. By exploiting unused timing margin, produced by state-of-the-art worst-case designs, energy efficiency is significantly increased. In-situ delay monitoring is performed by enhanced flip-flops, observing signal delays in critical paths. We introduce a novel methodology to analyze the closed-loop behavior of the overall control scheme by a Markov approach, based on extensive transistor simulations. The digital logic and the AVS control circuitry are designed in 65nm CMOS for an image processing application. The AVS approach optimizes dynamic and leakage power dependent on the user-defined image quality requirements.

Original language	English
Title of host publication	Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012
Pages	205-208
Number of pages	4
DOIs	https://doi.org/10.1109/DDECS.2012.6219058
State	Published - 2012
Event	2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012 - Tallinn, Estonia Duration: 18 Apr 2012 → 20 Apr 2012

Publication series

Name	Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012

Conference

Conference	2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012
Country/Territory	Estonia
City	Tallinn
Period	18/04/12 → 20/04/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/DDECS.2012.6219058

Cite this

Wirnshofer, M., Heiß, L., Kakade, A. N., Aryan, N. P., Georgakos, G., & Schmitt-Landsiedel, D. (2012). Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012 (pp. 205-208). Article 6219058 (Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012). https://doi.org/10.1109/DDECS.2012.6219058

Wirnshofer, Martin ; Heiß, Leonhard ; Kakade, Anil Narayan et al. / Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit. Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012. 2012. pp. 205-208 (Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012).

@inproceedings{f7630bb93b3d4fcbaf91f6df051167b2,

title = "Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit",

abstract = "The proposed voltage scheme adaptively tunes the supply voltage of digital circuits, according to PVTA variations. By exploiting unused timing margin, produced by state-of-the-art worst-case designs, energy efficiency is significantly increased. In-situ delay monitoring is performed by enhanced flip-flops, observing signal delays in critical paths. We introduce a novel methodology to analyze the closed-loop behavior of the overall control scheme by a Markov approach, based on extensive transistor simulations. The digital logic and the AVS control circuitry are designed in 65nm CMOS for an image processing application. The AVS approach optimizes dynamic and leakage power dependent on the user-defined image quality requirements.",

author = "Martin Wirnshofer and Leonhard Hei{\ss} and Kakade, \{Anil Narayan\} and Aryan, \{Nasim Pour\} and Georg Georgakos and Doris Schmitt-Landsiedel",

year = "2012",

doi = "10.1109/DDECS.2012.6219058",

language = "English",

isbn = "9781467311854",

series = "Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012",

pages = "205--208",

booktitle = "Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012",

note = "2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012 ; Conference date: 18-04-2012 Through 20-04-2012",

}

Wirnshofer, M, Heiß, L, Kakade, AN, Aryan, NP, Georgakos, G & Schmitt-Landsiedel, D 2012, Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit. in Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012., 6219058, Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012, pp. 205-208, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012, Tallinn, Estonia, 18/04/12. https://doi.org/10.1109/DDECS.2012.6219058

Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit. / Wirnshofer, Martin; Heiß, Leonhard; Kakade, Anil Narayan et al.
Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012. 2012. p. 205-208 6219058 (Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit

AU - Wirnshofer, Martin

AU - Heiß, Leonhard

AU - Kakade, Anil Narayan

AU - Aryan, Nasim Pour

AU - Georgakos, Georg

AU - Schmitt-Landsiedel, Doris

PY - 2012

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N2 - The proposed voltage scheme adaptively tunes the supply voltage of digital circuits, according to PVTA variations. By exploiting unused timing margin, produced by state-of-the-art worst-case designs, energy efficiency is significantly increased. In-situ delay monitoring is performed by enhanced flip-flops, observing signal delays in critical paths. We introduce a novel methodology to analyze the closed-loop behavior of the overall control scheme by a Markov approach, based on extensive transistor simulations. The digital logic and the AVS control circuitry are designed in 65nm CMOS for an image processing application. The AVS approach optimizes dynamic and leakage power dependent on the user-defined image quality requirements.

AB - The proposed voltage scheme adaptively tunes the supply voltage of digital circuits, according to PVTA variations. By exploiting unused timing margin, produced by state-of-the-art worst-case designs, energy efficiency is significantly increased. In-situ delay monitoring is performed by enhanced flip-flops, observing signal delays in critical paths. We introduce a novel methodology to analyze the closed-loop behavior of the overall control scheme by a Markov approach, based on extensive transistor simulations. The digital logic and the AVS control circuitry are designed in 65nm CMOS for an image processing application. The AVS approach optimizes dynamic and leakage power dependent on the user-defined image quality requirements.

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U2 - 10.1109/DDECS.2012.6219058

DO - 10.1109/DDECS.2012.6219058

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SN - 9781467311854

T3 - Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012

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Wirnshofer M, Heiß L, Kakade AN, Aryan NP, Georgakos G, Schmitt-Landsiedel D. Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012. 2012. p. 205-208. 6219058. (Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2012). doi: 10.1109/DDECS.2012.6219058

Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit

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