Accelerating system-level design Tasks using Commodity graphics hardware: A case study

Unmesh D. Bordoloi, Samarjit Chakraborty

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-hard). As a result, they involve high running times even for mid-sized problems. In this paper we explore the possibility of using commodity graphics processing units (GPUs) to accelerate such tasks that commonly arise in the electronic design automation (EDA) domain. We demonstrate this idea via a detailed case study on a general hardware/software design space exploration problem and propose a GPU-based engine for it. Not only does this problem commonly arise in the embedded systems domain, its computational kernel turns out to be a general combinatorial optimization problem (viz. the knapsack problem) which lies at the heart of several EDA applications. Our experimental results show that our GPU-based implementation offers very attractive speedups for this computational kernel (up to 100×), and speedups of up to 17× for the full problem. In contrast to ASIC/FPGA-based accelerators - since even low-end desktop and notebook computers are today equipped with GPUs - our solution involves no extra hardware cost. Although recent research has shown the benefits of using GPUs for a variety of non-graphics applications (e.g. in databases and bioinformatics), hardly any work has been done on harnessing the parallelism of GPUs to accelerate problems from the EDA domain. We hope that our results and the generality of the problem we address will motivate researchers from this community to explore the possibility of using GPUs for a wider variety of problems from the EDA domain.

Original languageEnglish
Title of host publicationProceedings
Subtitle of host publication22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
Pages465-470
Number of pages6
DOIs
StatePublished - 2009
Externally publishedYes
Event22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems - New Delhi, India
Duration: 5 Jan 20099 Jan 2009

Publication series

NameProceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems

Conference

Conference22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
Country/TerritoryIndia
CityNew Delhi
Period5/01/099/01/09

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