Accelerating packet buffering and administration in network processors

The steady increase of processing requirements in today's networks has led to the introduction of network processors (NPs) as a new class of application-specific integrated circuits. NPs are multiprocessor devices specialized for delivering both high packet processing performance and programming flexibility. Their throughput depends not only on the processing resources but also on the memory subsystem performance, since supporting elevated line speeds typically requires an excessive amount of data transfers to and from the memory. Our work focuses on the optimization of the memory access scheme in NPs. In this paper we present a hardware implementation of a buffer manager coprocessor, which not only stores/retrieves the packets autonomously to/from the memory, but also manages the packet memory, thereby completely off-loading these tasks from the processing cluster. We describe the memory data structures, the device architecture and implementation of the Buffer Manager on an FPGA. We evaluate our coprocessor in a platform with a CPU running a standard IP forwarding software and compare it with a reference architecture where packet administration is done in software. The results show that our coprocessor highly benefits the overall system performance both in terms of packet rate and data throughput.