TY - GEN
T1 - A versatile sampling ADC system for on-detector applications and the advancedTCA crate standard
AU - Mann, Alexander
AU - Konorov, Igor
AU - Paul, Stephan
PY - 2007
Y1 - 2007
N2 - A data acquisition system based on sampling analog to digital converters (ADCs) and data processing in field programmable gate arrays (FPGAs) is presented. Up to 32 ADC channels are combined with reconfigurable logic on a small mezzanine form factor card to get a handy module for analog data acquisition. This module can then be mounted either on a dedicated detector frontend or included in an Advanced Telecom Computing Architecture (ATCA) crate system. For on-detector usage the system provides several features for fail safe and also fail tolerant operation and data readout. This opens applications in high energy physics detectors with difficult access schemes to the electronic part. The crate system offers on the other hand a high channel density with moderate channel costs. Additionally, the ATCA standard provides enough data bandwidth for online data processing within the crate system. Due to the unified interface of the ADC mezzanine cards, the system cost can be further reduced by an easy up- or downgrade of the ADC sampling frequency or the channel count by exchanging just the mezzanine card and thus maintaining the whole surrounding infrastructure. This enables to serve different detector requirements with a limited number of different mezzanine card types and eases also further enhancements with new upcoming ADC or FPGA devices.
AB - A data acquisition system based on sampling analog to digital converters (ADCs) and data processing in field programmable gate arrays (FPGAs) is presented. Up to 32 ADC channels are combined with reconfigurable logic on a small mezzanine form factor card to get a handy module for analog data acquisition. This module can then be mounted either on a dedicated detector frontend or included in an Advanced Telecom Computing Architecture (ATCA) crate system. For on-detector usage the system provides several features for fail safe and also fail tolerant operation and data readout. This opens applications in high energy physics detectors with difficult access schemes to the electronic part. The crate system offers on the other hand a high channel density with moderate channel costs. Additionally, the ATCA standard provides enough data bandwidth for online data processing within the crate system. Due to the unified interface of the ADC mezzanine cards, the system cost can be further reduced by an easy up- or downgrade of the ADC sampling frequency or the channel count by exchanging just the mezzanine card and thus maintaining the whole surrounding infrastructure. This enables to serve different detector requirements with a limited number of different mezzanine card types and eases also further enhancements with new upcoming ADC or FPGA devices.
UR - https://www.scopus.com/pages/publications/85075815225
U2 - 10.1109/RTC.2007.4382804
DO - 10.1109/RTC.2007.4382804
M3 - Conference contribution
AN - SCOPUS:85075815225
SN - 1424408679
SN - 9781424408672
T3 - 2007 15th IEEE-NPSS Real-Time Conference, RT
BT - 2007 15th IEEE-NPSS Real-Time Conference, RT
PB - IEEE Computer Society
T2 - 2007 15th IEEE-NPSS Real-Time Conference, RT
Y2 - 29 April 2007 through 4 May 2007
ER -