A tightly coupled and hierarchical multiprocessor architecture

W. Händler; A. Bode; G. Fritsch; W. Henning; J. Volkert

doi:10.1016/0010-4655(85)90139-0

A tightly coupled and hierarchical multiprocessor architecture

W. Händler, A. Bode, G. Fritsch, W. Henning, J. Volkert

Friedrich Alexander Universität Erlangen-Nürnberg

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

The Erlangen General Purpose Array (EGPA) consists of a grid-like array of memory-coupled processor-modules. Above the array there is a hierarchy of processors for supervising and for data transports. An experimental pilot pyramid was realized. For a broad spectrum of applications the measured efficiency of the 4 worker-processors of the pilot pyramid ranged between 80 and 100%.

Original language	English
Pages (from-to)	87-93
Number of pages	7
Journal	Computer Physics Communications
Volume	37
Issue number	1-3
DOIs	https://doi.org/10.1016/0010-4655(85)90139-0
State	Published - Jul 1985
Externally published	Yes

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10.1016/0010-4655(85)90139-0

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title = "A tightly coupled and hierarchical multiprocessor architecture",

abstract = "The Erlangen General Purpose Array (EGPA) consists of a grid-like array of memory-coupled processor-modules. Above the array there is a hierarchy of processors for supervising and for data transports. An experimental pilot pyramid was realized. For a broad spectrum of applications the measured efficiency of the 4 worker-processors of the pilot pyramid ranged between 80 and 100%.",

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AU - Bode, A.

AU - Fritsch, G.

AU - Henning, W.

AU - Volkert, J.

PY - 1985/7

Y1 - 1985/7

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AB - The Erlangen General Purpose Array (EGPA) consists of a grid-like array of memory-coupled processor-modules. Above the array there is a hierarchy of processors for supervising and for data transports. An experimental pilot pyramid was realized. For a broad spectrum of applications the measured efficiency of the 4 worker-processors of the pilot pyramid ranged between 80 and 100%.

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A tightly coupled and hierarchical multiprocessor architecture

Abstract

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