A test design method for floating gate defects (FGD) in analog integrated circuits

Michael Pronath, Helmut Graeb, Kurt Antreich

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the sets of undetectable values of the trapped charge on the floating gate transistor It covers all potential gate charges of an FGD at one or more transistors and allows the application of conventional circuit simulators for simulating DC, AC and transient test. Based on this fault simulation, a test design methodology is presented that can determine all test sets that detect all FGDs for all possible values of gate charge.

Original languageEnglish
Article number998252
Pages (from-to)78-83
Number of pages6
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
StatePublished - 2002
Event2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France
Duration: 4 Mar 20028 Mar 2002

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