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A test concept for circuit level aging demonstrated by a differential amplifier

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations

Abstract

In this work a general concept for accelerated aging of linear analog circuit blocks is proposed. Due to the interaction of diverse aging mechanisms, circuit behavior in an arbitrary effect accelerated stress setup may show large deviation to the aging under nominal circuit conditions. The proposed analytical small signal analysis proves to be a fast and easy way to obtain the contributions of all degrading transistors with respect to the output monitor of the circuit. Circuit aging simulations over temperature rise as well as supply and input voltage scaling show that single effect acceleration varies significantly between the involved mechanisms. This causes deviations in the aging output monitor compared to the aging under nominal circuit conditions. Based on these findings an accelerated circuit level aging test concept - applicable to linear circuits - is developed and evaluated for the example of a two-stage differential amplifier.

Original languageEnglish
Title of host publication2010 IEEE International Reliability Physics Symposium, IRPS 2010
Pages826-829
Number of pages4
DOIs
StatePublished - 2010
Event2010 IEEE International Reliability Physics Symposium, IRPS 2010 - Garden Grove, CA, Canada
Duration: 2 May 20106 May 2010

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference2010 IEEE International Reliability Physics Symposium, IRPS 2010
Country/TerritoryCanada
CityGarden Grove, CA
Period2/05/106/05/10

Keywords

  • Aging acceleration
  • Circuit reliability
  • Degradation
  • HCI
  • NBTI
  • PBTI
  • Testing

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